Multi-level Cell Research Articles

Synaptic array using multi-level AND flash memory cells for hardware-based neural networks

We propose an AND array architecture in which bit-lines (BLs) and source-lines (SLs) of thin film transistor (TFT)-type flash memory cells used as synapses are arranged in parallel, and show the fabricated device and array characteristics. A top gate dielectric stack and a bottom gate dielectric stack serve to store a synaptic weight and select excitatory or inhibitory synapses, respectively. Multi-level (>5-bit) synaptic weight states and selective write operations in the AND array architecture are achieved by utilizing a simple update pulse scheme. Furthermore, weighted sum operation in a fabricated 9 × 3 AND flash synaptic array is successfully carried out by measuring BL currents when input pulses are applied to multiple word-lines (WLs) for hardware-based neural networks (HNNs).

Architecting Optically Controlled Phase Change Memory

Phase Change Memory (PCM) is an attractive candidate for main memory, as it offers non-volatility and zero leakage power while providing higher cell densities, longer data retention time, and higher capacity scaling compared to DRAM. In PCM, data is stored in the crystalline or amorphous state of the phase change material. The typical electrically controlled PCM (EPCM), however, suffers from longer write latency and higher write energy compared to DRAM and limited multi-level cell (MLC) capacities. These challenges limit the performance of data-intensive applications running on computing systems with EPCMs. Recently, researchers demonstrated optically controlled PCM (OPCM) cells with support for 5 bits / cell in contrast to 2 bits / cell in EPCM. These OPCM cells can be accessed directly with optical signals that are multiplexed in high-bandwidth-density silicon-photonic links. The higher MLC capacity in OPCM and the direct cell access using optical signals enable an increased read/write throughput and lower energy per access than EPCM. However, due to the direct cell access using optical signals, OPCM systems cannot be designed using conventional memory architecture. We need a complete redesign of the memory architecture that is tailored to the properties of OPCM technology. This article presents the design of a unified network and main memory system called COSMOS that combines OPCM and silicon-photonic links to achieve high memory throughput. COSMOS is composed of a hierarchical multi-banked OPCM array with novel read and write access protocols. COSMOS uses an Electrical-Optical-Electrical (E-O-E) control unit to map standard DRAM read/write commands (sent in electrical domain) from the memory controller on to optical signals that access the OPCM cells. Our evaluation of a 2.5D-integrated system containing a processor and COSMOS demonstrates 2.14 × average speedup across graph and HPC workloads compared to an EPCM system. COSMOS consumes 3.8× lower read energy-per-bit and 5.97× lower write energy-per-bit compared to EPCM. COSMOS is the first non-volatile memory that provides comparable performance and energy consumption as DDR5 in addition to increased bit density, higher area efficiency, and improved scalability.

Parallelism-Aware Channel Partition for Read/Write Interference Mitigation in Solid-State Drives

The advancement of multi-level cell technology that enables storing multiple bits in a single NAND flash memory cell has increased the density and affordability of solid-state drives (SSDs). However, increased latency asymmetry between read and write (R/W) intensifies the severity of R/W interference, so reads cannot be processed for a long time owing to the extended flash memory resource occupancy of writing. Existing flash translation layer (FTL)-level mitigation techniques can allocate flash memory resources in a balanced manner taking R/W interference into account; however, due to the inefficient utilization of parallel flash memory resources, the effect on performance enhancement is restrictive. From the perspectives of the predicted access pattern and available concurrency of flash memory resources, we propose a parallelism-aware channel partition (PACP) scheme that prevents SSD performance degradation caused by R/W interference. Moreover, an additional performance improvement is achieved by reallocating interference-vulnerable page using leveraged garbage collection (GC) migration. The evaluation results showed that compared with the existing solution, PACP reduced the average read latency by 11.6% and average write latency by 6.0%, with a negligible storage overhead.

A shared page-aware machine learning assisted method for predicting and improving multi-level cell NAND flash memory life expectancy

NAND flash memory is widely used in consumer electronics, personal computers, and enterprise data storage servers. The most prevalent source of flash memory errors is retention errors, which are mainly caused by leakage of charges. It has been observed that inside the chip, some flash memory blocks exhibit greater endurance to the retention errors than others. In an effort to prolong life expectancy, previous studies focus on improving the Raw Bit Error Rate (RBER) metric at page and block levels, without due consideration of the geometry of shared pages. In this paper, the first insight we provide is that groups of shared pages have different RBER values, and should be analyzed separately. We use this insight to construct a machine learning model to predict the blocks which have less endurance, using the characterization data of new unused flash memory chip(s). This is accomplished by extracting location-sensitive and value-sensitive features from the shared pages group, and engineering them into more sophisticated and explainable features. Furthermore, we describe how our proposed prediction model can be used in combination with the existing flash translation layer (FTL) wear-leveling algorithm to increase lifetime. We evaluated the proposed prediction and lifetime improvement method for four different machine learning techniques, among which Support Vector Machine (SVM) achieved superior accuracy up to 85% at a lower computational overhead.

A novel ferroelectric nanopillar multi-level cell memory

In this work, we present a novel multi-level non-volatile memory (NVM) device where ferroelectric (FE) nanopillars are embedded in a dielectric (DE) medium. Using our in-house 3D phase field simulator developed to treat the FE–DE composite system stably, we demonstrate that n FE nanopillars can generate more than 2n states, enabling high storage capacity. The multistates of the pillar array device are attributed to the depolarization field modulation with the pillar height and the multi-domain topological states of nanoscale FE structures.

Double magnetic tunnel junction two bit memory and nonvolatile logic for in situ computing

In exascale computing, a huge amount of data is processed in real-time. Conventional CMOS-based computing paradigms follow the read, compute, and write back mechanism. This approach consumes significant power and time to compute and store data. in situ computation – where data are processed within the memory system – is considered a platform for exascale computation. Spin transfer torque perpendicular magnetic tunnel junctions (PMTJ) is a nonvolatile memory device with several potential advantages (fast read/write, high endurance, and CMOS compatibility) to become a next generation memory solution. A double magnetic tunnel junction (DMTJ) consists of two PMTJs constructed in a vertical arrangement. In this paper, DMTJ offers the possibility of constructing not only standalone and embedded RAM but also MTJ-based VLSI computing. A DMTJ-based two bit memory cell that supports a nonvolatile logic compute paradigm is presented. The multi-level cell supports both a high speed read/write two bit memory cell and a nonvolatile logic gate that computes and stores input data in real-time.

Data Representation Aware of Damage to Extend the Lifetime of MLC NAND Flash Memory

Multilevel cell (MLC) NAND flash memory uses the voltages of the memory cells to represent bits, but high voltages cause much more damage on the cells than low voltages. Free space in MLC can be leveraged to reduce the usage of the high voltages and thus extend the lifetime of MLC. However, limited by the conventional data representation rule that represents bits by the voltage of one single cell, the high voltages are used in a high probability. To fully explore the potential of the free space on reducing the usage of high voltages without changing the total density of MLC, we propose a novel data representation aware of damage, named DREAM. DREAM uses the low voltage combinations of multiple cells instead of the voltage of one single cell to represent bits. It enables to represent the same bits through flexibly replacing the high voltages in some cells with the low voltages in other cells when free space is available. Hence, high voltages which cause more damage are less used and the lifetime of the MLC memory is extended. In addition, complementary techniques are proposed to mitigate performance loss induced by DREAM. Theoretical analysis and simulation results demonstrate the effectiveness and efficiency of DREAM.

Adaptive Mode Transformation for Wear Leveling in Nonvolatile FPGAs

Nowadays, field programmable gate arrays (FPGAs) have been widely adopted to serve as accelerators in artificial intelligence and big data related applications. Since the static random access memory (SRAM)-based FPGA is suffering from limited density and high leakage power, nonvolatile FPGAs have been proposed, where SRAM is replaced with emerging nonvolatile memories (NVMs). Multilevel cell (MLC), which can store multiple bits within one memory cell, further improves the density of nonvolatile FPGAs and shows great potential to enable large on-chip memory. However, it suffers from limited lifetime. In this article, we propose a wear leveling scheme to improve lifetime of MLC-based nonvolatile FPGAs. Instead of generating a series of configuration files for runtime reconfiguration, we propose to identify write-heavy MLC regions and dynamically transform them to durable single-level cell (SLC) mode. Specifically, we propose three modules: 1) pertaining to write behavior monitor; 2) approximate cost calculator; and 3) mode transformation manager to achieve adaptive mode transformations. We consider FPGA features to design these modules, which is different from implementations for MLC-SLC transformation in CPU architecture. Evaluation shows that the proposed scheme can improve lifetime for MLC nonvolatile FPGAs by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6.03\times $ </tex-math></inline-formula> , at cost of 12.5% storage overhead.

Hybrid RRAM/SRAM in-Memory Computing for Robust DNN Acceleration

RRAM-based in-memory computing (IMC) effectively accelerates deep neural networks (DNNs) and other machine learning algorithms. On the other hand, in the presence of RRAM device variations and lower precision, the mapping of DNNs to RRAM-based IMC suffers from severe accuracy loss. In this work, we propose a novel hybrid IMC architecture that integrates an RRAM-based IMC macro with a digital SRAM macro using a programmable shifter to compensate for the RRAM variations and recover the accuracy. The digital SRAM macro consists of a small SRAM memory array and an array of multiply-and-accumulate (MAC) units. The nonideal output from the RRAM macro, due to device and circuit nonidealities, is compensated by adding the precise output from the SRAM macro. In addition, the programmable shifter allows for different scales of compensation by shifting the SRAM macro output relative to the RRAM macro output. On the algorithm side, we develop a framework for the training of DNNs to support the hybrid IMC architecture through ensemble learning. The proposed framework performs quantization (weights and activations), pruning, RRAM IMC-aware training, and employs ensemble learning through different compensation scales by utilizing the programmable shifter. Finally, we design a silicon prototype of the proposed hybrid IMC architecture in the 65-nm SUNY process to demonstrate its efficacy. Experimental evaluation of the hybrid IMC architecture shows that the SRAM compensation allows for a realistic IMC architecture with multilevel RRAM cells (MLCs) even though they suffer from high variations. The hybrid IMC architecture achieves up to 21.9%, 12.65%, and 6.52% improvement in post-mapping accuracy over state-of-the-art techniques, at minimal overhead, for ResNet-20 on CIFAR-10, VGG-16 on CIFAR-10, and ResNet-18 on ImageNet, respectively.

Design space exploration for balanced MLC-PCM programming

Multi-Level Cell Phase Change Memory (MLC PCM) is a non-volatile memory technology that promises high-density data storage. However, MLC PCM suffers from long write latency because changing the state of each memory cell takes a long time and the number of cells that can be written concurrently is limited due to the relatively large size and power consumption of the write drivers. MLC PCM typically divides the write data into multiple cell groups to program cells in batches. The group mapping has a significant impact on the overall latency of write requests. Prior work proposed a group mapping technique for single-level cell (SLC) PCM based on the data pattern of a set of applications. In this work, a larger design space of group mapping is explored for MLC PCM. The specific group mapping for each benchmark is dynamically customized. Our technique leads to a 13.14% reduction in write latency compared to the state-of-the-art method (Du et al., 2013) and shows good temporal consistence in different benchmarks.

Resistive Switching Characteristics of Alloyed AlSiOx Insulator for Neuromorphic Devices

Charge-based memories, such as NAND flash and dynamic random-access memory (DRAM), have reached scaling limits and various next-generation memories are being studied to overcome their issues. Resistive random-access memory (RRAM) has advantages in structural scalability and long retention characteristics, and thus has been studied as a next-generation memory application and neuromorphic system area. In this paper, AlSiOx, which was used as an alloyed insulator, was used to secure stable switching. We demonstrate synaptic characteristics, as well as the basic resistive switching characteristics with multi-level cells (MLC) by applying the DC sweep and pulses. Conduction mechanism analysis for resistive switching characteristics was conducted to understand the resistive switching properties of the device. MLC, retention, and endurance are evaluated and potentiation/depression curves are mimicked for a neuromorphic device.

Process Optimization to Reduce Power in HfO2-Based Rram Devices for in-Memory Computing

Recently, HfO2-based resistive random-access memory (RRAM) devices have shown promise as candidates for in-memory computing applications. By engineering the distribution of defects or oxygen vacancies, the switching dielectric can potentially enable low power switching and multi-conductance levels. A higher concentration of oxygen vacancies closer to the top electrode a two-terminal RRAM device with a HfO2/Al2O3 bilayer structure reduces switching energy (1). Introducing excess oxygen vacancies near the top electrode through a hydrogen plasma treatment with a Ru as top electrode reduces the switching power of the device (2).In this work we study the pulsed SET operation of different HfO2-based RRAM devices for their possible uses as multi-level cells. We have compared two different RRAM devices with HfO2-based dielectrics. Device-A is prepared with hydrogen plasma treatment at mid-point of HfO2 deposition (10nm Ti/50nmTiN/3nm HfO2(plasma treatment) 3nm HfO2/5nm Ru/5nm ALD TiN/ 50nm PVD TiN). Whereas Device-B constitutes a HfO2/Al2O3 bilayer structure (10nm Ti/50nmTiN/7nm HfO2/1nm Al2O3/5nm Ru/5nm ALD TiN/50nm PVD TiN). Both the devices have Ru as the top metal.Fig. 1 and Fig. 2 show the conductance modulation obtained by applying successive pulse sequences (80 pulses) with increasing the pulse width tp (from 4 \U0001d707s to 10 ms) every 20 pulses where the pulse height, Vp, remained fixed at 2V during the experiment. A read pulse with voltage Vr=0.1V and pulse width tr=1ms is applied immediately after each pulse. The forming compliance current in Device-A is seven time lower than Device-B. Both devices clearly show promising behavior of multi-level conductance. Figure 1

Rebirth-FTL: Lifetime Optimization via Approximate Storage for NAND Flash Memory

The lifetime of NAND flash cells significantly degrades with feature-size reductions and multilevel cell technology. On the other hand, we have more and more approximate data, such as images and videos that are more error tolerant than regular data like text. In this article, we propose Rebirth-FTL, which reuses faulty blocks that contain uncorrectable errors to store approximate data for lifetime optimization. Rebirth-FTL effectively manages two spaces, namely, the approximate space and the normal space, with an efficient address translator, a coordinated garbage collection, and a differential wear leveler. In addition, we develop an migration times restriction (MTR) policy to restrict the movement of the approximate data in the approximate space. We also develop a scheme to pass approximate information from userland to kernel space in Linux. Finally, a lifetime model is presented for lifetime analysis. Our experimental results show that Rebirth-FTL can extend the lifetime by 41.63% on average.

Multi-level Cells and Quantized Conductance Characteristics of Al2O3-Based RRAM Device for Neuromorphic System

Recently, various resistance-based memory devices are being studied to replace charge-based memory devices to satisfy high-performance memory requirements. Resistance random access memory (RRAM) shows superior performances such as fast switching speed, structural scalability, and long retention. This work presented the different filament control by the DC voltages and verified its characteristics as a synaptic device by pulse measurement. Firstly, two current–voltage (I–V) curves are characterized by controlling a range of DC voltages. The retention and endurance for each different I–V curve were measured to prove the reliability of the RRAM device. The detailed voltage manipulation confirmed the characteristics of multi-level cell (MLC) and conductance quantization. Lastly, synaptic functions such as potentiation and depression, paired-pulse depression, excitatory post-synaptic current, and spike-timing-dependent plasticity were verified. Collectively, we concluded that Pt/Al2O3/TaN is appropriate for the neuromorphic device.

A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References

Resistive random access memory (RRAM)-based compute-in-memory (CIM) has shown great potential for accelerating deep neural network (DNN) inference. However, device characteristics, such as low-resistance values, susceptibility to drift, and single-level cells, may limit the capabilities of RRAM-based CIM. In addition, prior works generally used the off-chip write-verify scheme to tighten RRAM resistance distributions and used off-chip analog-to-digital converter (ADC) references for fine-tuning partial sum quantization. Although off-chip techniques are viable for testing purposes, they may be unsuitable for practical applications. In this work, we present an RRAM-CIM macro to accelerate DNN inference. The chip features: 1) multi-level cell (MLC) RRAM for improving compute performance and density; 2) sparsity-aware input control to leverage the high activation sparsity in DNN models; 3) on-chip write-verify to speed up initial weight programming and periodically refresh cells to compensate for resistance drift under stress; and 4) on-chip ADC reference generation that provides column-wise tunability and stability with varying temperatures to guarantee the CIFAR-10 accuracy of 85.8% at 120 °C. The design is fabricated in TSMC 40-nm process with embedded RRAM technology and achieves a macro-level peak performance of 97.8 GOPS/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 44.5 TOPS/W for multiply-and-accumulate (MAC) operations on VGG-8 network with ternary weights.

Atomic Layer Deposited SiOX-Based Resistive Switching Memory for Multi-Level Cell Storage

Herein, stable resistive switching characteristics are demonstrated in an atomic-layer-deposited SiOX-based resistive memory device. The thickness and chemical properties of the Pt/SiOX/TaN stack are verified by transmission electron microscopy (TEM) and X-ray photoemission spectroscopy (XPS). It is demonstrated that much better resistive switching is obtained using a negative set and positive reset compared to the opposite polarity. In addition, multi-level switching is demonstrated by changing the compliance current (CC) and the reset stop voltage, and potentiation and depression are emulated by applying pulses to achieve a synaptic device. Finally, a pulse endurance of 10,000 cycles and a retention time of 5000 s are confirmed by modulating the pulse input and reading voltage, respectively.

ZnSnOy/ZnSnOx Bilayer Transparent Memristive Synaptic Device for Neuromorphic Computing

In this letter, we have investigated synaptic features of a transparent bilayer memristor for neuromorphic computing applications. Our device has shown stable synaptic characteristics like potentiation and depression for repetitive 5000 epochs having 400 conductance pulses each. The device has also shown highly linear synaptic features with linearity of 1.2 and −1.4 for potentiation and depression, respectively. Retention property of bilayer transparent synapse showed good stability for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{{5}}$ </tex-math></inline-formula> s at 90 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\text {o}}\text{C}$ </tex-math></inline-formula> . Multi-Level Cell (MLC) characteristics were achieved by varying reset stop voltages from −0.7V to −1.0V. The proposed bilayer transparent synapse showed good synaptic characteristics and showed high potential to be used in future neuromorphic computing systems.

Recent developments in phase‐change memory

AbstractPhase‐change memory (PCM) belongs to the nonvolatile solid‐state memory techniques. Usually, a chalcogenide is sandwiched between two conductive electrodes and data are stored by setting each cell to a low‐resistance (crystalline) or a high‐resistance (amorphous) state. Switching between these states is relatively fast, which makes phase‐change random access memories (PCRAMs) highly interesting for nonvolatile memories. Multilevel cells, which can store more than 1 bit per cell, and multilayer high‐density memory arrays have also been reported as advantages of PCRAM. Writing currents and data retention, on the other hand, still show potential for optimization. This review gives an overview of the most recent developments in new material compositions and material‐related optimization of PCM in comparison with already produced PCM.

Unipolar resistive switching behavior in MoS2–polyvinyl alcohol-based memory device

MoS2–polymer-based memory devices have attracted significant interest owing to their mechanical flexibility, convenient solution processability, and affordability. These devices exhibit bipolar resistive switching behavior, and their switching relies on the polarity of the applied bias. This paper presents a memory device in which a MoS2–polyvinyl alcohol (PVA) hybrid film is sandwiched between Ag and Pt electrodes. The developed Ag/MoS2–PVA/Pt device manifests typical unipolar resistive switching (URS) behavior and nonvolatile rewritable memory performance with a low operating voltage, large ON/OFF ratio (105), and multilevel cell storage ability. Notably, 1T-phase MoS2 is crucial for the URS behavior, and this switching behavior can be ascribed to the charge trapping as well as the Joule-heating-induced de-trapping of the S vacancies associated with 1T MoS2. These findings can facilitate the development of new designs for high-performance, high-density data storage.

IGZO CIM: Enabling In-Memory Computations Using Multilevel Capacitorless Indium–Gallium–Zinc–Oxide-Based Embedded DRAM Technology

Compute-in-memory (CIM) is a promising approach for efficiently performing data-centric computing (such as neural network computations). Among the multiple semiconductor memory technologies, embedded DRAM (eDRAM), which integrates the DRAM bit cell with high-performance logic transistors, can enable efficient CIM designs. However, the silicon-based eDRAM technology suffers from poor retention time-incurring significant refresh power overhead. However, eDRAM using back-end-of-line (BEOL) integrated <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C$ </tex-math></inline-formula> -axis aligned crystalline (CAAC) indium–gallium–zinc–oxide (IGZO) transistors, exhibiting extreme low leakage, is a promising memory technology with lower refresh power overhead. A long retention time in IGZO eDRAM can enable multilevel cell functionality, which can improve its efficacy in CIM applications. In this article, we explore a capacitorless IGZO eDRAM-based multilevel cell, capable of storing 1.5 bits/cell for CIM designs focused on deep neural network (DNN) inference applications. We perform a detailed design space exploration of IGZO eDRAM sensitivity to process temperature variations for read, write, and retention operations followed by architecture-level simulations comparing performance and energy for different workloads. The effectiveness of IGZO eDRAM-based CIM architecture is evaluated using a representative neural network, and the proposed approach achieves 82% Top-1 inference accuracy for the CIFAR-10 dataset, compared with 87% software accuracy with high bit cell storage density.