Multi-level Cell Research Articles

Scaling Effect on Silicon Nitride Memristor with Highly Doped Si Substrate.

A feasible approach is reported to reduce the switching current and increase the nonlinearity in a complementary metal-oxide-semiconductor (CMOS)-compatible Ti/SiNx /p+ -Si memristor by simply reducing the cell size down to sub-100 nm. Even though the switching voltages gradually increase with decreasing device size, the reset current is reduced because of the reduced current overshoot effect. The scaled devices (sub-100 nm) exhibit gradual reset switching driven by the electric field, whereas that of the large devices (≥1 µm) is driven by Joule heating. For the scaled cell (60 nm), the current levels are tunable by adjusting the reset stop voltage for multilevel cells. It is revealed that the nonlinearity in the low-resistance state is attributed to Fowler-Nordheim tunneling dominating in the high-voltage regime (≥1 V) for the scaled cells. The experimental findings demonstrate that the scaled metal-nitride-silicon memristor device paves the way to realize CMOS-compatible high-density crosspoint array applications.

A joint-LDPC decoding scheme based on retention error characteristics for MLC NAND flash memory

With the aggressive scaling and the Multi-Level Cell (MLC) technology, the reliability of NAND flash degrades seriously. Therefore, the traditional error correction schemes are becoming less and less effective. Low-Density Parity-Check (LDPC) code and soft-decision memory sensing will be more suitable in the next generation Error Correction Code (ECC) technologies for MLC NAND flash memory. However, LDPC ECC schemes have their own bottleneck due to the unacceptably long read latency during the decoding scheme. The read latency primarily includes two aspects: repeated read cycles and iterative belief-propagation decoding. Motivated by the precise probability information can improve the performance of LDPC decoding, we propose a novel Joint-LDPC (J-LDPC) scheme to reduce the decoding latency of LDPC ECC. The key idea of the proposed J-LDPC scheme is to introduce a new calculating method of probability information in a pair of shared flash pages, according to the retention error characteristics of MLC NAND flash rather than several reading operations. Through a large amount of experiments from our own hardware-software co-designed experimental platform, compared with the traditional soft-decision LDPC scheme, the proposed J-LDPC scheme can reduce the average iterations of LDPC decoder by 50% and enhance the error correction strength by 58%.

Neuron inspired data encoding memristive multi-level memory cell

Mapping neuro-inspired algorithms to sensor backplanes of on-chip hardware require shifting the signal processing from digital to the analog domain, demanding memory technologies beyond conventional CMOS binary storage units. Using memristors for building analog data storage is one of the promising approaches amongst emerging non-volatile memory technologies. Recently, a memristive multi-level memory cell for storing discrete analog values has been developed in which memory system is implemented combining memristors in voltage divider configuration. In given example, the memory cell of 3 sub-cells with a memristor in each was programmed to store ternary bits which overall achieved 10 and 27 discrete voltage levels. However, for further use of proposed memory cell in analog signal processing circuits data encoder is required to generate control voltages for programming memristors to store discrete analog values. In this paper, we present the design and performance analysis of data encoder that generates write pattern signals for 10 level memristive memory.

An SLC-Like Programming Scheme for MLC Flash Memory

Although the multilevel cell (MLC) technique is widely adopted by flash-memory vendors to boost the chip density and lower the cost, it results in serious performance and reliability problems. Different from past work, a new cell programming method is proposed to not only significantly improve chip performance but also reduce the potential bit error rate. In particular, a single-level cell (SLC)-like programming scheme is proposed to better explore the threshold-voltage relationship to denote different MLC bit information, which in turn drastically provides a larger window of threshold voltage similar to that found in SLC chips. It could result in less programming iterations and simultaneously a much less reliability problem in programming flash-memory cells. In the experiments, the new programming scheme could accelerate the programming speed up to 742% and even reduce the bit error rate up to 471% for MLC pages.

Performance analysis of three-dimensional-triple-level cell and two-dimensional-multi-level cell NAND flash hybrid solid-state drives

In order to improve performance of solid-state drives (SSDs), hybrid SSDs have been proposed. Hybrid SSDs consist of more than two types of NAND flash memories or NAND flash memories and storage-class memories (SCMs). However, the cost of hybrid SSDs adopting SCMs is more expensive than that of NAND flash only SSDs because of the high bit cost of SCMs. This paper proposes unique hybrid SSDs with two-dimensional (2D) horizontal multi-level cell (MLC)/three-dimensional (3D) vertical triple-level cell (TLC) NAND flash memories to achieve higher cost-performance. The 2D-MLC/3D-TLC hybrid SSD achieves up to 31% higher performance than the conventional 2D-MLC/2D-TLC hybrid SSD. The factors of different performance between the proposed hybrid SSD and the conventional hybrid SSD are analyzed by changing its block size, read/write/erase latencies, and write unit of 3D-TLC NAND flash memory, by means of a transaction-level modeling simulator.

An Analysis of Flash Page Reuse With WOM Codes

Flash memory is prevalent in modern servers and devices. Coupled with the scaling down of flash technology, the popularity of flash memory motivates the search for methods to increase flash reliability and lifetime. Erasures are the dominant cause of flash cell wear, but reducing them is challenging because flash is a write-once medium— memory cells must be erased prior to writing. An approach that has recently received considerable attention relies on write-once memory (WOM) codes, designed to accommodate additional writes on write-once media. However, the techniques proposed for reusing flash pages with WOM codes are limited in their scope. Many focus on the coding theory alone, whereas others suggest FTL designs that are application specific, or not applicable due to their complexity, overheads, or specific constraints of multilevel cell (MLC) flash. This work is the first that addresses all aspects of page reuse within an end-to-end analysis of a general-purpose FTL on MLC flash. We use a hardware evaluation setup to directly measure the short- and long-term effects of page reuse on SSD durability and energy consumption, and show that FTL design must explicitly take them into account. We then provide a detailed analytical model for deriving the optimal garbage collection policy for such FTL designs, and for predicting the benefit from reuse on realistic hardware and workload characteristics.

Express Read in MLC Phase Change Memories

In the era of big data, the capability of computer systems must be enhanced to support 2.5 quintillion byte/day data delivery. Among the components of a computer system, main memory has a great impact on overall system performance. DRAM technology has been used over the past four decades to build main memories. However, the scalability of DRAM technology has faced serious challenges. To keep pace with the ever-increasing demand for larger main memory, some new alternative technologies have been introduced. Phase change memory (PCM) is considered as one of such technologies for substituting DRAM. PCM offers some noteworthy properties such as low static power consumption, nonvolatility, and capability of storing more than one bit per cell (multilevel cell, or MLC). However, the short lifetime and long access latency of PCM (specifically MLC PCM) require feasible and efficient solutions. In this article, based on the observation that applications access a significant number of read-friendly data blocks, we propose Express Read to prevent the MLC PCM read circuit to spend unnecessary time sensing the cells of a memory block. A read-friendly data block (RFDB) is composed of only “11” and “00” bit pairs, and thus upon sensing the most significant bit of a cell, the read operation can be early terminated to reduce the MLC read time and power consumption. Moreover, we increase the number of RFDBs using two simple techniques to better exploit the benefits of Express Read. Results obtained from full-system simulation near 6% performance improvement and 21% energy gain, on average, over the baseline system.

Analysis on applicable error-correcting code strength of storage class memory and NAND flash in hybrid storage

A hybrid of storage class memory (SCM) and NAND flash is a promising technology for high performance storage. Error correction is inevitable on SCM and NAND flash because their bit error rate (BER) increases with write/erase (W/E) cycles, data retention, and program/read disturb. In addition, scaling and multi-level cell technologies increase BER. However, error-correcting code (ECC) degrades storage performance because of extra memory reading and encoding/decoding time. Therefore, applicable ECC strength of SCM and NAND flash is evaluated independently by fixing ECC strength of one memory in the hybrid storage. As a result, weak BCH ECC with small correctable bit is recommended for the hybrid storage with large SCM capacity because SCM is accessed frequently. In contrast, strong and long-latency LDPC ECC can be applied to NAND flash in the hybrid storage with large SCM capacity because large-capacity SCM improves the storage performance.

Effect of conductance linearity and multi-level cell characteristics of TaOx-based synapse device on pattern recognition accuracy of neuromorphic system

To improve the classification accuracy of an image data set (CIFAR-10) by using analog input voltage, synapse devices with excellent conductance linearity (CL) and multi-level cell (MLC) characteristics are required. We analyze the CL and MLC characteristics of TaOx-based filamentary resistive random access memory (RRAM) to implement the synapse device in neural network hardware. Our findings show that the number of oxygen vacancies in the filament constriction region of the RRAM directly controls the CL and MLC characteristics. By adopting a Ta electrode (instead of Ti) and the hot-forming step, we could form a dense conductive filament. As a result, a wide range of conductance levels with CL is achieved and significantly improved image classification accuracy is confirmed.

Improved Synapse Device With MLC and Conductance Linearity Using Quantized Conduction for Neuromorphic Systems

In this letter, we demonstrate the conductive-bridging RAM (CBRAM) with excellent multi-level cell (MLC) and linear conductance characteristics for an artificial synaptic device of neuromorphic systems. Our findings show that inherent characteristics of CBRAM can achieve the linear conductance and MLC characteristics as a product of an integer unit of the conductance. However, uncontrolled metal-ion injection into the switching layer results in a significant degradation of device uniformity, leading to degradation in the classification accuracy. Thus, we introduce a multi-layer CBRAM configuration (Cu/HfO2/Ta/Cu2S/W) to control the ionic motion in electrolytes. As a result of device engineering, highly improved classification accuracy is achieved using CIFAR-10 data set.

Efficient LDPC Code Design for Combating Asymmetric Errors in STT-RAM

Spin-transfer torque random access memory (STT-RAM) is a promising emerging memory technology in the future memory hierarchy. However, its unique reliability challenges, i.e., the asymmetric bit failure mechanism at different bit flippings, have raised significant concerns in its real applications. Recent studies even show that the common memory error repair “remedies” cannot efficiently address them. In this article, we for the first time systematically study the potentials of the strong low-density parity-check (LDPC) code for combating such unique asymmetric errors in both single-level-cell (SLC) and multi-level-cell (MLC) STT-RAM designs. A generic STT-RAM channel model suitable for the SLC/MLC designs, is developed to analytically calibrate all the accumulated asymmetric factors of the write/read operations. The key initial information for LDPC decoding, namely asymmetric log-likelihood ratio (A-LLR), is redesigned and extracted from the proposed channel model, to unleash the LDPC’s asymmetric error correcting capability. LDPC codec is also carefully designed to lower the hardware cost by leveraging the systematic-structured parity check matrix. Then two customized short-length LDPC codes—(585,512) and (683,512)—augmented from the semi-random parity check matrix and the A-LLR based asymmetric decoding, are proposed for SLC and MLC STT-RAM designs, respectively. Experiments show that our proposed LDPC designs can improve the STT-RAM reliability by at least 10 2 (10 4 ) when compared to the existing error correction codes (ECCs) for the SLC (MLC) design, demonstrating the feasibility of LDPC solutions on STT-RAM.

LLR-Distribution-Based Non-Uniform Quantization for RBI-MSD Algorithm in MLC Flash Memory

Multi-level cell (MLC) technique has been widely used to improve the storage capacity of NAND flash memory at the price of sacrificing some storage reliability. As a type of excellent error-correction codes, low-density parity-check (LDPC) codes can significantly enhance the performance of flash memory. However, the conventional decoding algorithms for LDPC codes suffer from the drawback of high complexity. To address this problem, we propose a serial reliability-based iterative min-sum decoding (RBI-MSD) algorithm for LDPC-coded MLC flash memory systems to strike a desirable trade-off between the performance and complexity. Furthermore, we conceive a novel log-likelihood-ratio (LLR)-distribution-based non-uniform quantization method for the RBI-MSD algorithm. Unlike conventional quantization methods, the proposed non-uniform quantization method substantially exploits the distribution characteristics of channel initial LLRs in MLC flash memory. Simulation results indicate that the proposed non-uniform quantization method not only exhibits more excellent error performance than the conventional non-uniform and uniform counterparts, but also is applicable to other RBI decoding algorithms.

Characteristics of multilevel storage and switching dynamics in resistive switching cell of Al2O3/HfO2/Al2O3 sandwich structure

We reported an Al2O3/HfO2/Al2O3 sandwich structure resistive switching device with significant improvement of multilevel cell (MLC) operation capability, which exhibited that four stable and distinct resistance states (one low resistance state and three high resistance states) can be achieved by controlling the Reset stop voltages (VReset-stop) during the Reset operation. The improved MLC operation capability can be attributed to the RHRS/RLRS ratio enhancement resulting from increasing of the series resistance and decreasing of leakage current by inserting two Al2O3 layers. For the high-speed switching applications, we studied the initial switching dynamics by using the measurements of the pulse width and amplitude dependence of Set and Reset switching characteristics. The results showed that under the same pulse amplitude conditions, the initial Set progress is faster than the initial Reset progress, which can be explained by thermal-assisted electric field induced rupture model in the oxygen vacancies conductive filament. Thus, proper combination of varying pulse amplitude and width can help us to optimize the device operation parameters. Moreover, the device demonstrated ultrafast program/erase speed (10 ns) and good pulse switching endurance (105 cycles) characteristics, which are suitable for high-density and fast-speed nonvolatile memory applications.

Improvement of multi-level resistive switching characteristics in solution-processed AlOx-based non-volatile resistive memory using microwave irradiation

We fabricated a resistive random access memory (ReRAM) device on a Ti/AlOx/Pt structure with solution-processed AlOx switching layer using microwave irradiation (MWI), and demonstrated multi-level cell (MLC) operation. To investigate the effect of MWI power on the MLC characteristics, post-deposition annealing was performed at 600–3000 W after AlOx switching layer deposition, and the MLC operation was compared with as-deposited (as-dep) and conventional thermally annealing (CTA) treated devices. All solution-processed AlOx-based ReRAM devices exhibited bipolar resistive switching (BRS) behavior. We found that these devices have four-resistance states (2 bits) of MLC operation according to the modulation of the high-resistance state (HRSs) through reset voltage control. Particularly, compared to the as-dep and CTA ReRAM devices, the MWI-treated ReRAM devices showed a significant increase in the memory window and stable endurance for multi-level operation. Moreover, as the MWI power increased, excellent MLC characteristics were exhibited because the resistance ratio between each resistance state was increased. In addition, it exhibited reliable retention characteristics without deterioration at 25 °C and 85 °C for 10 000 s. Finally, the relationship between the chemical characteristics of the solution-processed AlOx switching layer and BRS-based multi-level operation according to the annealing method and MWI power was investigated using x-ray photoelectron spectroscopy.

Exploiting Approximate MLC-PCM in Low-Power Embedded Systems

Multi-level cell phase change memory (MLC-PCM), because of its very low leakage power and high density, is promising for embedded systems. Furthermore, for applications with inherent low sensitivity to errors, approximate write operations can be exploited in MLC-PCM to improve endurance and performance. However, data that reside in the approximate MLC-PCM for a rather long time without refreshing are prone to soft errors due to resistance drift phenomenon, while even for an application with inherent low sensitivity to errors, a high soft error rate can degrade its Quality of Result (QoR). The architecture-level approaches to decrease the drift effect incur considerable power overhead (about 100%), which is a prominent issue in embedded systems, and are dependent on the number of logic levels stored in the PCM cell (e.g., most of them are designed for 4LC-PCM). This article, taking a different approach, proposes a drift-aware frequency and voltage management to alleviate the drift-based soft-error rate. To this end, first we characterize the application data based on the degree of being exposed to the drift to identify the drift-prone application data. Then we assign the execution frequency and voltage to different regions of the application considering the drift. This frequency assignment speeds up the application regions wherein the drift-prone data are accessed to shorten the lifetime of the drift-prone data, thereby decreasing the soft error rate. An integer linear programming model implements our proposed Dynamic Voltage Frequency Scaling (DVFS). Also, the proposed approach is independent of the number of levels of PCM cells and can be applied to any MLC-PCM system. To evaluate the approach, the approximate MLC-PCM is simulated using empirical models and is integrated into a full-system simulator as data memory. The experimental results show that, by exploiting the approach, QoR is in the acceptable range, while its power overhead is about 84% (on average) less than that of the architecture-level approach.

State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers

Multilevel Cell Spin-Transfer Torque Random Access Memory (MLC STT-RAM) is a promising nonvolatile memory technology to build registers for its natural immunity to electromagnetic radiation in rad-hard space environment. Unlike traditional SRAM-based registers, MLC STT-RAM exhibits unbalanced write state transitions due to the fact that the magnetization directions of hard and soft domains cannot be flipped independently. This feature leads to nonuniform costs of write states in terms of latency and energy. However, current SRAM-targeting register allocations do not have a clear understanding of the impact of the different write state-transition costs. As a result, those approaches heuristically select variables to be spilled without considering the spilling priority imposed by MLC STT-RAM. Aiming to address this limitation, this paper proposes a state-transition-aware spilling cost minimization (SSCM) policy, to save power when MLC STT-RAM is employed in register design. Specifically, the spilling cost model is first constructed according to the linear combination of different state-transition frequencies. Directed by the proposed cost model, the compiler picks up spilling candidates to achieve lower power and higher performance. Experimental results show that the proposed SSCM technique can save energy by 19.4% and improve the lifetime by 23.2% of MLC STT-RAM-based register design.

GCMix

In multi-level cell (MLC) NAND flash memory, two logical pages are overlapped on a single physical page. Even after a logical page is programmed, the data can be corrupted if the programming of the coexisting logical page is interrupted. This phenomenon is called paired page interference. This article proposes a novel software technique to deal with the paired page interference without any additional hardware or extra page write. The proposed technique utilizes valid pages in the victim block during garbage collection (GC) as the backup against the interference, and pairs them with incoming pages written by the host. This approach eliminates undesirable page copy to backup pages against the interference. However, such a strategy has an adverse effect on the hot/cold separation policy, which is essential to improve the efficiency of GC. To limit the downside, we devise a metric to estimate the benefit of GCMix on-the-fly so that GCMix can be adaptively utilized only when the benefit outweighs the overhead. Evaluations using synthetic and real workloads show GCMix can effectively deal with the paired page interference, reducing the write amplification factor by up to 17.5%compared to the traditional technique, while providing comparable I/O performance.

Novel Operation of a Multi-Bit SOT Memory Cell Addressed With a Single Write Line

Spin–orbit torque (SOT) originates from the spin–orbit interaction of non-magnetic heavy metals (HMs), allowing for an electrical manipulation of perpendicular magnetization in HM/ferromagnet (FM)/oxide structures. In this paper, we experimentally demonstrate the SOT-induced switching of two FM bits addressed with a single write line. We fabricate a device consisting of two perpendicularly magnetized Ta/CoFeB/MgO structures with a common Ta underlayer, in which the magnetization directions of the two FM bits could be concurrently controlled by injecting a single current pulse. This suggests that multiple bits in SOT-based devices can be written as either “0” or “1” at the same time. Moreover, the selective switching of a specific bit is achieved by differentiating the critical switching currents between the two FM bits, which is crucial in demonstrating multi-level cell SOT memory. Our results provide an efficient writing mechanism, enabling wider applications of SOT-based spintronic devices.

HL-PCM: MLC PCM Main Memory with Accelerated Read

Multi-Level Cell Phase Change Memory (MLC PCM) is a promising candidate technology for DRAM replacement in main memory of modern computers. Despite of its high density and low power advantages, this technology seriously suffers from slow read and write operations. While prior works extensively studied the problem of slow write, this paper targets high read latency problem in MLC PCM and introduces an architecture mechanism to overcome it. To this end, we rely on the fact that reading different bits from an MLC cell takes different latencies, i.e., for a 2-bit MLC, reading its Most-Significant Bit (MSB) is fast, while reading its Least-Significant Bits (LSBs) is slower. We then propose Half-Line PCM (HL-PCM), a novel memory architecture that leverages this non-uniformity in reading MLC PCM’s content to send a requested memory block to the processor in different cycles–it sends half of a memory block to the processor ahead of the other half. If the processor requested a word belonging to the first half, it can resume its execution on receiving the first half, while the other half has not sent yet and scheduled to be received by the memory controller later. HL-PCM is easy and simple to implement, i.e., it needs minor modifications at memory controller, the search/evict policies at last level cache, as well as data layout in main memory. Our experimental results show that the proposed design improves the average memory access latency by 33–43 percent and program’s execution time by 23 percent, on average, while incurring negligible overhead at memory controller and PCM DIMM, in a 16-core chip multiprocessor (CMP) running memory-intensive benchmarks.

Flying Capacitor Multilevel Inverter Control Considering Lower Order Harmonics Elimination Based on Newton-Raphson Algorithm

Newton-Raphson-based flying capacitor multilevel inverter modeling is investigated for capacitor voltage balancing. Without using voltage feedback, Newton-Raphson method determines the best switching pattern for maintaining nil mean current in all capacitors, hence minimizing the capacitor voltage fluctuation and eliminating certain harmonic orders. Flying capacitor multilevel inverter (FCMI) modeling is developed to work with the selective harmonic elimination (SHE) technique to obtain a programmable pulse generator for multilevel inverter commutation cell control. Theoretical results are verified by experiments and simulations for a flying capacitor four-level inverter. Results show that the proposed method does effectively eliminate a number of specific low order harmonics, and the output voltage is resulted in low total harmonic distortion and with balanced flying capacitors.