Multilayer Interconnects Research Articles

Reliability of LSI multilayer interconnects

Reliability of LSI multilayer interconnects

Molecular Beam Epitaxy Growth of High Mobility Compound Semiconductor Devices for Integration with Si CMOS

AbstractWe report on a direct epitaxial growth approach for the heterogeneous integration of high speed III-V devices with Si CMOS logic on a common Si substrate. InP-based heterojunction bipolar transistor (HBTs) structures were successfully grown on patterned Si-on-Lattice-Engineered-Substrate (SOLES) substrates using molecular beam epitaxy. DC and RF performance similar to those grown on lattice-matched InP were achieved in growth windows as small as 15×15μm2. This truly planar approach allows tight device placement with InP-HBTs to Si CMOS transistors separation as small as 2.5 μm, and the use of standard wafer level multilayer interconnects. A high speed, low power dissipation differential amplifier was designed and fabricated, demonstrating the feasibility of using this approach for high performance mixed signal circuits such as ADCs and DACs.

Process development in metal/BCB multilayer interconnections of MMCM with embedded chip in Si substrate

A vertical interlayer connection via (VILCV) fabrication process is presented. This process is used for the interconnection of multilayer benzocyclobutene (BCB) based microwave multichip modules (MMCM). The excellent planarity of BCB allows VILCV to be formed using gold electroplating or stud bumps prior to BCB application. And mechanical polishing (MP) planarization is adopted to expose the VILCV, enabling interconnection between different layers. Subsequently upper interconnection is patterned. Metal/BCB multilayer structure can be made by repeating above steps. This approach eliminates the need for laser drilling and plasma etching. Both four terminal Kelvin structures and via chains are fabricated as test vehicles. Finally, a transition of transmission lines in different layers and a packaged MMIC embedded in Si substrate are presented and measured in high frequency range up to 20 GHz. The results show there is only minimal performance degradation.

Copper polishing with a polishing pad incorporating abrasive grains and a chelating resin

This study sought to decrease dishing and erosion as they cause reduced yield in copper chemical mechanical polishing (Cu-CMP), which is a multilayer interconnect process that is a part of the overall semiconductor manufacturing process. We prepared a polishing pad that incorporated abrasive grains (AC Pad) and used a chelating resin in the matrix (resin). Moreover, we studied whether this polishing pad was applicable to the Cu-CMP process. Results indicated that the pad was selectively abrasive to copper (Cu) and that in the polishing of patterned wafers, it vastly decreased dishing to 1/8th and erosion to half of their respective levels in abrasive polishing. Therefore, the pad has considerable potential for use in Cu-CMP.

A Finite-Element Domain-Decomposition Methodology for Electromagnetic Modeling of Multilayer High-Speed Interconnects

The complicated geometry of high-density interconnect structures in multilayer, planar substrates is one of the major hurdles in the application of finite element methods for their multigigahertz electromagnetic analysis. In addition to compounding the complexity in the generation of the finite element grid, the multilayer nature of the structures and their multiscale attributes result in finite element systems of very large dimension which, more often than not, are not well conditioned. This paper presents a domain decomposition methodology for overcoming these hurdles. More specifically, the proposed methodology utilizes the multiple power and ground planes used in such structures as natural physical boundaries for their decomposition into a set of subdomains, each one of which is meshed and discretized separately from the rest. The electromagnetic interaction between the domains is effected through the enforcement of tangential field continuity conditions at the voids and via holes present at the power and ground planes. In particular, a Krylov subspace model order reduction approach is used to facilitate the broadband solution of the multilayer interconnect structure. The proposed modeling methodology is demonstrated through its application to the electromagnetic analysis of several multilayer interconnect structures.

Inkjet printed System-in-Package design and manufacturing

Additive manufacturing technology using inkjet offers several improvements to electronics manufacturing compared to current non-additive masking technologies. Manufacturing processes can be made more efficient, straightforward and flexible compared to subtractive masking processes, several time-consuming and expensive steps can be omitted. Due to the additive process, material loss is minimal, because material is never removed as with etching processes. The amounts of used material and waste are smaller, which is advantageous in both productivity and environmental means. Furthermore, the additive inkjet manufacturing process is flexible allowing fast prototyping, easy design changes and personalization of products. Additive inkjet processing offers new possibilities to electronics integration, by enabling direct writing on various surfaces, and component interconnection without a specific substrate. The design and manufacturing of inkjet printed modules differs notably from the traditional way to manufacture electronics. In this study a multilayer inkjet interconnection process to integrate functional systems was demonstrated, and the issues regarding the design and manufacturing were considered.

Efficient Full-Wave Analysis of Multilayer Interconnection Structures Using a Novel Domain Decomposition–Model-Order Reduction Method

A novel domain decomposition-model-order reduction method is proposed for efficient full-wave finite-element analysis of multilayer interconnection structures. By considering the special properties of a multilayer structure, the field at each nonmetallic interface (via-holes or other apertures) can be approximated with a modal expansion to establish a boundary condition and decompose the entire computational domain into separate layers. The coupling between each dielectric layer is taken into account through a mode-matching process. To further speed up the computation in each layer, the solution space projection, which is a multipoint model-order reduction method, is integrated into the aforementioned domain decomposition method to form a complete solution algorithm. With the aid of reduced-order models, the domain decomposition process at each frequency is accelerated and a fast broadband analysis is achieved. This domain decomposition-model-order reduction method, called approximate modal interface-solution space projection, is implemented using the finite-element method and validated through several examples, which demonstrate the efficiency of the method in both the computation time and memory usage.

Tolerance Analysis for Multilayer Optical Interconnections Integrated on a Printed Circuit Board

Polymer multilayer optical interconnections have gained interest over the past few years in view of their ability to increase the integration density, increase the routing flexibility, and make full use of the characteristics of 2D optoelectronic elements. The alignment between the functional elements in the different optical layers has to be sufficiently accurate in ensuring a high overall efficiency of the system. Numerical simulations have been used as a tool to determine whether laser ablation can be used as an alternative technology for the structuring of the functional elements of optical interconnections into a polymer optical layer. The experimentally achievable alignment accuracies are compared to tolerance ranges for an excess loss ? 1 dB obtained from the numerical study. The experimental achievements show that the alignment accuracies fall within the numerical tolerance ranges and have a good reproducibility. Experimental realizations of a two-layer multimode waveguide and inter- and out-of-plane- coupling structures are discussed and shown.

Integration of 0/1-Level Packaged RF-MEMS Devices on MCM-D at Millimeter-Wave Frequencies

This paper reports on the development and optimization of 0/1-level packaged coplanar waveguide (CPW) lines and radio-frequency microelectromechanical systems (RF-MEMS) switches up to millimeter-wave frequencies. The 0-level package consists of an on-chip cavity obtained by flip-chip mounting a capping chip over the RF-MEMS device using BenzoCyclobutene (BCB) as the bonding and sealing material. The 0-level coplanar RF feedthroughs are implemented using BCB as the dielectric; gold stud-bumps and thermocompression are used for realizing the 1-level package. The 0-level packaged switches have been flip-chip mounted on a multilayer thin-film interconnect substrate using a high-resistivity Si carrier with embedded passives and substrate cavities. The insertion loss of a single 0/1-level transition is below -0.15 dB at 50 GHz. The measured return loss of a 0/1-level packaged 50-Omega CPW line remains better than -19 dB up to 71 GHz and better than -15 dB up to 90 GHz. It is shown that the leak rate of BCB sealed cavities depends on the BCB width, and leak rates as low as 10-11 mbar.l/s are measured for large BCB widths (> 800 mum), dropping to 10-8 mbar.l/s for BCB widths of around 100 mum. Depending on the bonding conditions, shear strengths as high as 150 MPa are achieved.

MLMIN: A multicore processor and parallel computer network topology for multicast

In future, multicore processors with hundreds of cores will collaborate on a single chip. Then, more advanced network-on-chip (NoC) topologies will be needed than today's shared busses for dual core processors. Multistage interconnection networks, which are already used in parallel computers, seem to be a promising alternative. In this paper, a new network topology is introduced that particularly applies to multicast traffic in multicore systems and parallel computers. Those multilayer multistage interconnection networks are described by defining the main parameters of such a topology. Performance and costs of the new architecture are determined and compared to other network topologies. Network traffic consisting of constant size packets and of varying size packets is investigated. It is shown that all kinds of multicast traffic particularly benefit from the new topology.

Brittle and Ductile Fracture Mechanics Analysis of Surface Damage Caused During CMP

This work reviews the mechanical properties and fracture mechanics of materials important in the manufacture of multilayer interconnects on silicon chips in order to understand surface damage caused during chemical mechanical polishing (CMP). It gives an explanation for chatter marks, surface flaking in interlayer dielectric material, and rolling indenter and plastic plow lines in copper on the wafer surface during CMP of silicon chips.

LTCC INTERCONNECT MODELING BY SUPPORT VECTOR REGRESSION

In this paper, we introduce a new method: support vector regression (SVR) method to modeling low temperature co-fired ceramic (LTCC) multilayer interconnect. SVR bases on structural risk minimization (SRM) principle, which leads to good generalization ability. A LTCC based stripline-to-stripline interconnect used as example to verify the proposed method. Experiment results show that the developed SVR model perform a good predictive ability in analyzing the electrical performance.

Design and Performance Modeling for Single-Walled Carbon Nanotubes as Local, Semiglobal, and Global Interconnects in Gigascale Integrated Systems

Based on physical models, distributed circuit models are presented for single-walled carbon nanotubes (SWCNs) and SWCN bundles that are valid for all voltages and lengths. These models can be used for circuit simulations and compact modeling. It is demonstrated that by customizing SWCN interconnects at the local, semiglobal, and global levels, several major challenges facing gigascale integrated systems can potentially be addressed. For local interconnects, monolayer or multilayer SWCN interconnects can offer up to 50% reduction in capacitance and power dissipation with up to 20% improvement in latency if they are short enough (<20 mum). For semiglobal interconnects, either latency or power dissipation can be substantially improved if bundles of SWCNs are used. The improvements increase as the cross-sectional dimensions scale down. For global interconnects, bandwidth density can be improved by 40% if there is at least one metallic SWCN per 3-nm2 cross-sectional area

Theoretical study of mechanical properties of multi-layer ULSI interconnect dielectrics by surface acoustic wave method

The surface acoustic waves (SAWs) technique is becoming an attractive tool for accurately and nondestructively characterizing the mechanical property of the fragile low dielectric constant (low-k) thin film used in the advanced ULSI multi-layer interconnects. The dispersion features of SAWs propagating on the layered structure of low-k/SiO2/Si substrate and low-k/Cu/Si substrate are investigated in detail. The influence of the film thickness on the dispersion curvature is provided as an instruction for an accurate and facile fitting process. Numerical results indicate that the mechanical property of low-k films is expected to determine effectively when the broadband frequency is up to 300MHz.

Realization of a microelectrofluidic platform

We report on the development of a low cost, manufacturing process for a threedimensional network, microelectrofluidic platform. The platform consists of multiple levels of fluidic channels and electrical circuits. The inter-level channels and circuits are connected through via holes and conductor-filled via holes respectively. The medium surrounding these channels and circuits is a polymeric material, in this case, PMMA. In this research, 2 separate chips have been made: a multi-layer fluidic network and a multi-layer electrical interconnect. The future goal would be to integrate both chips into one. The process involves the hot embossing of channels on thin sheets of PMMA and the deposition of metal circuits using the conductive paste printing technique. Both processes are low cost in terms of capital investment and in terms of raw materials used to make the chips. Backend processes include multi-layer bonding, via drilling, dicing and final assembly. A 4-layer fluidic network and a 4-layer electrical interconnect based on the PMMA substrate have been fabricated through a cheap and simple process. Testing shows fluidic and electrical transmission through the multi-layer chips.

Planar SOFC Stack with Low Cost Multi-layer Ceramic Interconnect

not Available.

P-71: Robust-Stretchable Interconnects for Flexible Display Applications

We report on a robust metallization scheme ideal for interconnects required in flexible display applications. Multi-layered metal interconnects including a granular discontinuous ductile indium layer, have been deposited on a variety of compliant substrates to confirm that there is a minimal change in resistance even when subjected to large mechanical strains and repeated low-strain fatigue loading. Initial analysis of deformed films also suggests there is a possibility for a self-healing process. A finite element analysis (FEA) model of the thin-metal film/polymer substrate structure, also confirms the stretchability of the granular indium islands observed to be bridging the cracked regions in the underlying conductive layers.

An All-Ceramic Interconnect for Use in Solid-Oxide Fuel Cell Stacks

AbstractThis article summarizes a unique approach in which all-ceramic interconnects are used in place of metal interconnects in solid-oxide fuel cell (SOFC) stacks. The approach combines advanced SOFC materials with the manufacturing technology and infrastructure established for multilayer ceramic (MLC) packaging for the microelectronics industry. The MLC interconnect is fabricated using multiple layers of yttria-stabilized zirconia (YSZ) tape, with each layer containing conductive vias to provide for electrical current flow through the interconnect. The all-ceramic interconnect design facilitates uniform distribution of air and fuel gas to the respective electrodes of adjacent cells. The multilayer interconnects are fabricated using traditional MLC manufacturing processes. A detailed description of the processes for fabricating the all-ceramic interconnect is presented.To aid in moving from prototype fabrication to commercialization of these fuel cell systems, a detailed cost model has been used as a roadmap for commercial stack development. Cost model projections are presented for three different interconnect footprint sizes. These projections show an SOFC stack cost of less than $150 per kilowatt for the optimized SOFC stack design produced at high volume.

Efficient Design of Integrated Antennas on Si for On-Chip Wireless Interconnects in Multi-Layer Metal Process

In this study it has been shown that the transmission gain of an integrated dipole antenna on a Si chip used for an on-chip wireless interconnect is drastically reduced in a multi-layer metal interconnect scheme when a second metal layer is placed above the antenna at the usual interlayer metal distance. The best way to preserve high gain of the integrated antenna in such a multi-layer metal process is to design an antenna with excitation vertically through the Si substrate. In the presence of the upper metal layers, the vertically excited field mode propagating through the Si substrate does not cause any significant reduction in the power transmission of the antenna. Simulations of the structures have been carried out using the ANSOFT high frequency structure simulation (HFSS) program employing the three dimensional finite element method. A simple analytical model has also been developed, and the results are presented for comparison.

Planar SOFC Stack with Low-Cost Multi-Layer Ceramic Interconnect

The SOFCo-EFS stack utilizes a multi-layer ceramic (MLC) interconnect that is designed to have a close thermal expansion match with zirconia-based cells. The MLC interconnect is fabricated using multiple layers of YSZ tape, with each layer containing conductive vias to provide for electrical current flow through the interconnect. Fuel and air supply to cells are accomplished through the use of flow passages in the layers. This paper provides an update on the development status for the MLC interconnects and stacks, with emphasis on low-cost conductor materials for the vias. Separate low-cost materials have been developed for the airside and fuel-side vias, and successfully implemented into 10 cm interconnects. Planar stacks have been assembled using electrolyte-supported cells and tested. Special instrumentation was used for these stacks in order to separate area specific resistance (ASR) contribution from each component.