Multilayer Interconnects Research Articles

Metal-printing tunable interlayer waveguide coupler using low-loss fluorinated polycarbonate.

Tunable three-dimensional (3D) integrated optical waveguide chips with optical interconnection function are beneficial to expand the application of optical devices in a 3D integrated photonic module. Here, we propose a thermo-optic (TO) tunable interlayer waveguide coupler based on the metal-printing technique. Low-loss fluorinated polycarbonate (AF-Ali-PC MA) and poly (methyl methacrylate-glycidyl methacrylate) [P(MMA-co-GMA)] are synthesized as waveguide core and cladding layer, respectively. The thermal stability and optical adsorption characteristics of AF-Ali-PC MA are analyzed. Optical signal transmission features of the interlayer coupling waveguides are simulated. The optical response properties and fabrication process flows of a dynamic multilayer waveguide chip can be greatly improved by the metal-printing technique. The on-off time of the TO interlayer coupling chip is obtained as 250 µs, and the electrical power consumption is measured as 7.6 mW. To the best of our knowledge, this is the first time that a TO tunable interlayer waveguide coupler is achieved by an efficient metal-printing method, which is suitable for large-scale photonic integrated circuit (PIC) systems and multilayer optical interconnection (OXC) networks.

Electrical resistivity evolution in electrodeposited Ru and Ru-Co nanowires

• Propose a strategy to reduce electrical resistivity and complexity of current interconnect structure in ICs. • Emulate a semiconductor metallization environment employing porous nano-templates. • Design nanoscale Ru and Ru-Co structures by electrodeposition. • Uncover electrical properties of Ru-based nanowires and microstructural evolution. Nanoscale ruthenium (Ru)-based materials are promising replacements for existing multilayered Cu interconnects in integrated circuits. However, it is not easy to apply the results of previously reported studies directly to the electrochemical damascene process because the previous studies have mainly focused on thin films by dry deposition. Here, we report the electrical resistivity and microstructure of electrodeposited Ru nanowires. We estimate that the resistivity value of a 10 nm diameter Ru nanowire to be 71.6 μΩ cm after analyzing the resistivity values of individual nanowires with various diameters. Furthermore, we investigate the electrical properties of Ru x Co 1- x nanowires where x is 0.04–0.99 at.% as possible replacements of the current TaN barrier structures. Over the entire composition range, the resistivity values of alloys are much lower than that of the conventional TaN. Additionally, Ru and Ru-alloy nanowires surrounded by dielectric silica are thermally stable after 450 °C heat treatment. Therefore, the nanoscale Ru and Ru-Co alloys possessing low resistivity values can be candidates for the interconnect and barrier materials, respectively.

Process-Recipe Development for Printing of Multilayer Circuitry With Z-Axis Interconnects Using Aerosol-Jet Printed Dielectric Vias

Abstract Flexible electronics is emerging as a new consumer-industry phenomenon. The promise of additively printed flexible electronics has sparked interest in a detailed understanding of the parameters and interactions of the printing process with the realized performance. Aerosol Jet printing technology has garnered increased interest, owing to a noncontact nature of print process and the high standoff allowing for printing on nonplanar surfaces. Prior efforts with aerosol-jet printing have focused on single-layer substrates. The current efforts focus on higher end printed circuit boards designs, which may need multilayers, with multilayer stacking of interconnections and z-axis connections through vias. The results presented in the paper attempt to address the need for process recipes for multilayer circuits and z-axis interconnects. Aerosol printing method has been shown to have wide compatibility with wide array of inks such as silver, copper, and carbon. Realization of high-volume scale-up of the process needs process recipes with statistical assessment of process stability and variance. In this paper, z-axis interconnects have been realized with the help of Aerosol printable silver ink and dielectric polyimide ink. The interaction of the sintering profile and the realized conductivity and shear load value of the printed conductive metal layers has been presented for each of the additional layers. Additive build-up processes may need successive exposure to temperature for the purpose of sintering. The downstream-printed conductive lines would undergo different sintering conditions and would then be tested for parameters such as interconnect resistance and shear load to failure. This paper explores the printing of multilayer up to eight conductive layers. Sintering profile for lower resistance per unit length and higher shear load to failure was tested.

(Invited) Area-Selective Atomic Layer Deposition for Interconnect Applications

As the semiconductor industry is approaching the 5nm node technology, conventional patterning schemes cannot meet the ever-increasing requirements for alignment imposed by device miniaturization. Area-Selective Deposition (ASD) can potentially alleviate such manufacturing challenges by enabling bottom-up material deposition. The most used and successful approach to achieve ASD envisage a combination of Atomic Layer Deposition (ALD) and surface passivation, such as, self-assembled monolayer (SAM).Among the potential applications, dielectric on dielectric (DoD) ASD emerged as one of the most important for multilayer nano interconnects (e.g.: enabling fully self-aligned vias). In this context, along with the difficulties encountered in preserving a confined material growth, the challenges extend to the fact that the deposited dielectric must exhibit well-defined properties, such as low-dielectric constant. Indeed, the integration an interconnect dielectric deposition process in an ASD scheme is arduous. Vapor-phase deposition of SiO2-like materials typically requires high process temperature as well as strong oxidants or O2-plasma. These are not compatible with the organic passivation films exploited to create well-distinguished local surface chemistries, which is essential to enable selective-material deposition.In this talk, 1-octadecanethiol (ODT) well-known selective chemisorption on Cu over SiO2 is exploited to achieve AS-DoD deposition and understand the surface-driven mechanism that enables a selective material growth. In addition, the proposed ASD scheme in combination with nanoscale adhesion force characterization is used to tackle a critical lack in ASD metrology: monitoring the passivation film directly on patterned substrate. Finally, the challenges and results obtained as an ODT-compatible dielectric deposition process for interconnect applications are discussed in this talk.ASD enabled by metal passivation for Hf3N4, Hf-Silicate, Al2O3, and Al-silicate ALD are explored and presented on Cu/SiO2 patterned substrates, with critical dimension as low as 10nm.

Evaluation of Chemical Bonding States in Multilayer Interconnect Structures for Thermal Management in Next Generation Very Large Scale Integration

1. Background and purpose Currently, it is expected that Ru is going to be introduced in place of Cu, which is the mainstream interconnect material in the very large scale integrated (VLSI) circuit. As high integration has been proceeding, the interconnect is expected not only having excellent electrical characteristics and reliability, but also providing an effective pathway for the removal of the heat generated by device operation [1]. The increasing current density in the narrowing interconnect produces Joule heat. The generated heat is removed by a heat sink attached to the substrate through the interconnect. Therefore, if the thermal resistance between the substrate and the interconnect is high, the heat cannot be removed efficiently and the interconnect temperature rises, lead to a degradation of VLSI reliability [2].In this study, we evaluated chemical bonding states of Ru/TaN/(SiOx/)Si stacking structure to clarify the mechanism contributing thermal resistance for the superior thermal management in VLSI. 2. Experimental method A 5 nm TaN was deposited by reactive sputtering (Deposition conditions: 25°C, 300 W, 1.0×10-5 Pa, Ta target) and subsequently 10 nm Ru was deposited by magnetron sputtering on a Si substrate with approximately 2 nm-thick native oxide. We prepared four samples with Ar:N2 gas ratios of 19:1, 17:3, 16:4, and 15:5, respectively, during the TaN deposition. The total thermal resistance was measured by the Frequency Domain Thermoreflectance (FDTR) method under vacuum condition.We also evaluated the chemical bonding states at the interface by Laboratory Hard X-ray Photoelectron Spectroscopy (Lab. HAXPES). The measurement conditions were kinetic energy of 9.25 keV, energy resolution of 0.5 eV, energy step of 50 meV, beam diameter of 50 μm2, and detectable depth of 50 nm, respectively. Au 4f was used as a reference of the energy calibration during for the analysis. 3. Results and Discussion The thermal resistance measured from the entire Ru/TaN/(SiOx/)Si stacking structure was reported by previous studies [1]. It can be seen that the thermal resistance decreases with the increase of N2 flow rate. In order to discuss the mechanism for determination of the thermal conductance, we performed nondestructive measurements by Lab. HAXPES.Figures 1 and 2 show the photoelectron spectra obtained from Ru 3d (Ar:N2=19:1, 15:5) and Si 1s (Ar:N2=19:1, 15:5), respectively. From Fig. 1, no significant change is observed in Ru 3d spectra even within the N2 gas flow rate changes. Therefore, the cause of the change in thermal resistance with the N2 gas flow rate change cannot be found at the Ru/TaN interface. On the other hand, from the Si 1s spectrum shown in Fig. 2, it can be confirmed that the peak intensity due to Si-N or Si-O-N bonds increases with increasing N2 gas flow rate. Therefore, it can be considered that the Si-N or Si-O-N bonds formed at the TaN/(SiOx/)Si interface as the N2 gas flow rate increased promoted heat transport and contributed to the reduction of thermal resistance.In summary, the important mechanism to control the thermal resistance became clear by the non-destructive evaluation of the chemical bonding states in the multilayer stacking structure using Lab. HAXPES. Acknowledgement This work was supported by the CREST under Project No. JPMJCR19Q5 of the Japan Science and Technology Corporation (JST).

Edge scattering limited crosstalk analysis in adjacent multilayer graphene interconnects and its impact on gate oxide reliability

PurposeThis paper aims to present the edge scattering dominant circuit modeling. The effect of crosstalk on gate oxide reliability (GOR), along with the mitigation using shielding technique is further studied.Design/methodology/approachAn equivalent distributed Resistance Inductance Capacitance circuit of capacitively coupled interconnects of multilayer graphene nanoribbon (MLGNR) has been considered for T Simulation Program with Integrated Circuit Emphasis (TSPICE) simulations under functional and dynamic switching conditions. Complementary metal oxide semiconductor driver transistors are modeled by high performance predictive technology model that drive the distributed segment with a capacitive load of 0.001 fF, VDD and clock frequency as 0.7 V and 0.2 GHz, respectively, at 14 nm technology node.FindingsThe results reveal that the crosstalk induced delay and noise area are dominated by the overall mean free path (MFP) (i.e. including the effect of edge roughness induced scattering), in contrary to, acoustic and optical scattering limited MFP with the temperature, width and length variations. Further, GOR, estimated in terms of average failure rate (AFR), shows that the shielding technique is an effective method to minimize the relative GOR failure rate by, 0.93e-7 and 0.7e-7, in comparison to the non-shielded case with variations in interconnect’s length and width, respectively.Originality/valueConsidering realistic circuit modeling for MLGNR interconnects by incorporating the edge roughness induced scattering mechanism, the outcomes exhibit more penalty in terms of crosstalk induced noise area and delay. The shielding technique is found to be an effective mitigating technique for minimizing AFR in coupled MLGNR interconnects.

Capacitance study of integrated circuits matrix interconnects

<span>Propagation delays and couplings between nearby lines affect the circuit performances (speed, power consumption) and operations. Propagation delays in longer lines can become critical compared to the clock frequency and can induce unwanted signals in neighboring lines ("crosstalk" phenomenon). Induced line capacitances can induce parasitic signals. Hence characterizing of these capacitances is of paramount importance. The present work deals with the analysis of capacitance of a multilayer conductor interconnect aiming for their possible exact extraction. We used three topologies of a microstrip conductor interconnects and identified the potential distributor and then computed the capacitance and inductance matrix using a finite element method. The first analysis dealt with parallel microstrip conductors and the second with two levels (plan) of a microstrip conductors the results are compared to those obtained by other methods and found quite encouraging.</span>

Direct Imaging of Integrated Circuits in CPU with 60 nm Super-Resolution Optical Microscope.

Far-field super-resolution optical microscopies have achieved incredible success in life science for visualization of vital nanostructures organized in single cells. However, such resolution power has been much less extended to material science for inspection of human-made ultrafine nanostructures, simply because the current super-resolution optical microscopies modalities are rarely applicable to nonfluorescent samples or unlabeled systems. Here, we report an antiphase demodulation pump-probe (DPP) super-resolution microscope for direct optical inspection of integrated circuits (ICs) with a lateral resolution down to 60 nm. Because of the strong pump-probe (PP) signal from copper, we performed label-free super-resolution imaging of multilayered copper interconnects on a small central processing unit (CPU) chip. The label-free super-resolution DPP optical microscopy opens possibilities for easy, fast, and large-scale electronic inspection in the whole pipeline chain for designing and manufacturing ICs.

Broadband Dielectric Behavior of an MIL-100 Metal–Organic Framework as a Function of Structural Amorphization

The performance of modern electronics is associated with the multi-layered interconnects, encouraging the development of a low-k dielectrics. Herein, we studied the effects of phase transition from crystalline to amorphous on dielectric, optical and electrical properties of MIL-100 (Fe) and Basolite F300 metal-organic framework (MOF) obtained using different synthesis techniques in both the radio (4-1.5 MHz) and infrared (1.2-150 THz) frequency regimes, which are important for the microelectronics, infrared optical sensors, and high-frequency telecommunications. The impact of amorphization on broadband dielectric response was established based on: (1) The comparison in the dielectric characteristics of a commercially available amorphous Basolite F300 versus a mechanochemically synthesized crystalline MIL-100 in the MHz region. (2) By tracking the frequency shifts in the vibrational modes of MIL-100 structure in the far-IR (phonons) and mid-IR regions. We showed that various parameters such as pelleting pressure, temperature, frequency, density, and degree of amorphization greatly affect the dielectric properties of the framework. We also investigated the influence of temperature (20-100 {\deg}C) on the electric and dielectric response in the MHz region, crucial for all electronic devices.

Effect of EDTA-based alkaline cleaning solution on TAZ removal in post CMP cleaning of copper interconnection

1,2,4-triazole (TAZ) has been proved to be an alternative to Benzotriazole (BTA) as an corrosion inhibitor in chemical mechanical polishing (CMP) of multilayer copper interconnection for integrated circuit. It has also become the main object to be removed in post CMP cleaning. In this paper, a new type of alkaline cleaning solution based on EDTA was proposed to remove TAZ on copper surface. The optimal concentration ratio and pH value of the alkaline cleaning solution were explored using electrochemical measurement, X-ray photoelectron spectroscopy (XPS) and atomic force microscopy (AFM) and scanning electron microscopy (SEM). When the components of the cleaning solution were 25mg/L ethylenediaminetetraacetic acid (EDTA) and 600mg/L dodecylbenzene sulfonic acid (LABSA) (pH = 10.6), the Cu-1,2,4-trazole compounds formed by TAZ contamination on the copper surface can be effectively removed. Density Functional Theory (DFT) was used to confirm that EDTA could break the bond of Cu-1,2,4-triazole through the strong interaction between O16、H2、H36 and copper surface. No corrosion was observed on the cleaned copper surface and surface roughness was lower, which indicated that the cleaning solution was suitable for the removal of TAZ on copper surface.

A compact LTCC semi‐lumped highpass filter with vialess structure

AbstractA new type of semi‐lumped highpass filter (HPF) based on multilayer technology is presented in this letter. Capacitive coupled stripline stubs are utilized as semi‐lumped resonators in the structure without using any means. Hence, undesired parasitic effect in the multilayer interconnections is minimized while high quality factor and stopband rejection are realized simultaneously. In this research, a HPF works from 5.15 to 5.95 GHz has been designed and fabricated on a low temperature cofired ceramic (LTCC) substrate. The proposed topology has been validated through a series of tests. By virtue of the LTCC multilayer technology, the proposed HPF is compact, occupying only a volume of 2.5 mm × 2.0 mm × 1.0 mm.

Crosstalk noise analysis in ternary logic multilayer graphene nanoribbon interconnects using shielding techniques

SummaryThis paper presents an accurate structure for multilayer graphene nanoribbon (MLGNR) bundled interconnects to reduce the effects of crosstalk in ternary logic circuits. In the proposed structures, the signal line is surrounded by the shielding lines to reduce the crosstalk effects. The crosstalk effects such as noise peak, noise area, delay, and power consumptions are compared to effects produced by conventional methods. The impacts of process variation in the proposed structures are also presented. Additionally, the proposed MLGNR interconnect results are compared with the carbon nanotube interconnections. All the proposed circuits are implemented and simulated using HSPICE tool. The simulation results indicated that the passively shielded MLGNR interconnects provide lower crosstalk effects up to 47.7% and 69.4%, respectively, over the active and without shielded interconnects.

패드 돌기의 기하학적 특성을 고려한 디바이스 패턴의 평탄화 모델링

Chemical mechanical planarization (CMP) is a semiconductor process which is necessary for multi-layer interconnection structure. CMP pad is a consumable used in the process and with numerous asperities on the surface that wear out by the load applied from the contact with the wafer. Also, it has a patterned wafer, the step height is gradually removed by contact of the asperities with upper and lower layers. The contact state would be different according to the step height reduction. Likewise, depending on the pattern size at the specific step height, the maximum radius of the asperity curvature differs whether it reaches the down area. In this study, the height distribution of asperities was expressed as a function of time and asperity height taking into account the wear of asperities, and based on the Greenwood-Williamson theory, a mathematical model for material removal rate considering pattern size was derived. The consistency of the novel model is verified with the CMP experiment conducted using oxide patterned wafers, and the experimental data were compared with the residual step height using theoretical removal rate. The root mean square error of the step height reduction was 19.84 nm.

Participation Patterns and Effectiveness of Out-of-School Time Mathematics Classes

Although shadowed by the institutionalization of contemporary schooling, out-of-school time and space encompass a variety of learning possibilities and are socially organized to enable and maintain educational privileges for some students but not for others. Out-of-school time (OST) curricular instructions have been expanding globally and more visible in East Asia. Relying on multilevel ordered logistic regression and generalized propensity score analysis; this study investigated the participation patterns and effectiveness of OST mathematics education in Shanghai, China. Family socioeconomic background and opportunity-to-learn indices of mainstream schooling were found to strongly link to participation in OST mathematics education. Higher socioeconomic status and more household resources were associated with higher likelihood of participating in OST mathematics education. Negative school-level opportunity-to-learn indices, such as problematic classroom disciplinary climate and insufficient mathematics instructional time, correlated with greater odds of OST mathematics participation. In addition, this study found a significant relationship between OST mathematics learning and mathematics study behaviors, with higher intensity of OST mathematics instruction triggering more positive study ethics and habits. Yet, no significant association between OST mathematics education and PISA mathematics achievement was identified. These findings profoundly illuminated the multi-layered interconnections between formal schooling and OST education and contributed to the discussions about structures of educational equality during out-of-school time.

Participation Patterns and Effectiveness of Out-of-School Time Mathematics Classes

Although shadowed by the institutionalization of contemporary schooling, out-of-school time and space encompass a variety of learning possibilities and are socially organized to enable and maintain educational privileges for some students but not for others. Out-of-school time (OST) curricular instructions have been expanding globally and more visible in East Asia. Relying on multilevel ordered logistic regression and generalized propensity score analysis; this study investigated the participation patterns and effectiveness of OST mathematics education in Shanghai, China. Family socioeconomic background and opportunity-to-learn indices of mainstream schooling were found to strongly link to participation in OST mathematics education. Higher socioeconomic status and more household resources were associated with higher likelihood of participating in OST mathematics education. Negative school-level opportunity-to-learn indices, such as problematic classroom disciplinary climate and insufficient mathematics instructional time, correlated with greater odds of OST mathematics participation. In addition, this study found a significant relationship between OST mathematics learning and mathematics study behaviors, with higher intensity of OST mathematics instruction triggering more positive study ethics and habits. Yet, no significant association between OST mathematics education and PISA mathematics achievement was identified. These findings profoundly illuminated the multi-layered interconnections between formal schooling and OST education and contributed to the discussions about structures of educational equality during out-of-school time.

Temperature‐dependent analysis of crosstalk and delay uncertainty in multilayer graphene nanoribbon interconnects

SummaryIn this article, we have analyzed delay uncertainty due to crosstalk in multilayer graphene nanoribbon (MLGNR) interconnects. Crosstalk is a challenging problem in deep‐sub‐micron and nanometer designs. In this work, we have analyzed the crosstalk delay with a wide variation in chip operating temperature. The mean free path is modeled as a function of temperature. Furthermore, the resistance of MLGNR interconnect system is modeled. Crosstalk delay analysis is performed for both top‐contact MLGNR and side‐contact MLGNR (SC‐MLGNR) interconnects and compared the results with that of the traditional Cu interconnects. The analysis has been carried out for different interconnect widths 11, 16, and 22 nm and lengths 10, 50, and 100 μm for three different chip operating temperatures 233, 300, and 398K. The decrease in rise/fall delay (speed up) and increase in rise/fall time delay (slow down) are modeled. Finally, the delay uncertainty is modeled for different interconnect systems. The percentage change in delay values for speed up and slow down cases are −23.4%, −29.8% and 114.4%, 161.9%, respectively, for 10μm SC‐MLGNR interconnect. It is shown that the delay uncertainty is significantly less in SC‐MLGNR interconnects and with the advancement of technology the performance is improved as compared with copper interconnects.

Low-cost and low-topography fabrication of multilayer interconnections for microfluidic devices

Multilayer interconnections are needed for microdevices with a large number of independent electrodes. A multi-level photolithographic process is commonly employed to provide multilayer interconnections in integrated circuit devices, but it is often too expensive for large-area or disposable devices frequently needed for microfluidics. The printed circuit board (PCB) can provide multilayer interconnection at low cost, but its rough topography poses a challenge for small droplets to slide over. Here we report a low-cost fabrication of low-topography multilayer interconnects by selective and controlled anodization of thin-film metal layers. The process utilizes anodization of metal (tantalum in this paper) or, more specifically, repetitions of a partial anodization to form insulation layers between conductive layers and a full anodization to form isolating regions between electrodes, replacing the usual process of depositing, planarizing, and etching insulation layers. After verifying the electric connections and insulations as intended, the developed method is applied to electrowetting-on-dielectric (EWOD), whose complex microfluidic products are currently built on PCB or thin-film transistor substrates. To demonstrate the utility, we fabricate a three metal-layer EWOD device with steps (surface topography) less than 1 micrometer (vs. > 10 micrometers of PCB EWOD devices) and confirm basic digital microfluidic operations.

The analytical model of frequency response and bandwidth for coupled multilayer graphene nanoribbon interconnects

This paper applies the multilayer graphene nanoribbons (MLGNR) as a prospective candidate material to replace the conventional copper (Cu) for next generation on-chip interconnects. Based on the equivalent single conductor (ESC) modeling, a distributed transmission line model for coupled MLGNR interconnects is presented to obtain the transfer gain and 3-dB bandwidth at the global level of 14 ​nm technology node, which take the in-phase and out-of-phase crosstalk modes into consideration, and verified with the Hspice simulation. It is demonstrated that the MLGNR and Cu interconnects under in-phase mode have a larger transfer gain and a wider 3-dB bandwidth than that under out-of-phase mode, and MLGNR interconnects can more effectively improve the transfer gain and 3-dB bandwidth compared with Cu interconnects at the same conditions. The numerical calculation results show that, decreasing interconnect temperature, increasing line space and increasing driver and load sizes are efficient ways to enhance the transfer gain and 3-dB bandwidth for MLGNR and Cu interconnects. Moreover, the top contact MLGNR (TC-MLGNR) also can be used as an emerging material for on-chip interconnects to replace the conventional Cu. In addition, it is found that the results obtained by the proposed model are in good matching with Hspice simulation and the maximum relative deviation for them is less than 4%, meanwhile the efficiency of CPU runtime is improved over 90% by using the proposed model, as compared to Hspice simulation. The results presented in this paper would be useful to design the on-chip interconnects with better bandwidth characteristics.

Performance and signal integrity analysis of intercalation‐doped MLVGNR interconnects

In this work, signal integrity, power consumption and stability of multilayer vertical graphene nanoribbon (MLVGNR) interconnects are determined and compared with multilayer horizontal GNR (MLHGNR) and conventional copper interconnects for different intercalation dopants and specularity indices. Lithium-intercalated MLVGNR outperforms these conventional interconnects in terms of delay. However, it is not very much immune to noise and also consumes more power but overall noise delay product and power delay product are least among all. As far as stability is concerned, MLVGNR interconnects have a comparable gain and phase margin and a steep transient response without an undershoot as compared with other interconnect configurations, which experience undershoot. It is worth to point out that MLVGNR interconnects are more amenable to scaling compared with other alternatives. This study for the first time analyses and compares the performance, signal integrity and stability of MLVGNR, MLHGNR and copper interconnects.

The insertion of high-k dielectric materials in multilayer graphene nanoribbon interconnects for reducing propagation delay and expanding bandwidth

Abstract The multilayer graphene nanoribbons (MLGNR) by inserting the high-k dielectric material between adjacent graphene nanoribbons (GNR) layers to reduce propagation delay and to expand bandwidth of the conventional pristine (undoped) MLGNR interconnects is presented in this paper. An equivalent distributed circuit model of the proposed MLGNR interconnect with high-k dielectric materials is established to derive the analytical expressions of propagation delay, step response, transfer gain and 3-dB bandwidth for 7.5 nm technology node at global level. The numerical simulation results show that the maximum reduction of propagation delay between the proposed MLGNR by inserting SrTiO3 dielectric material and the pristine MLGNR can reach 12.746 ns for an interconnect length of 4000 μm. The corresponding 3-dB bandwidth for them can be expanded over 4 times for the interconnect length. It is demonstrated that the proposed MLGNR by inserting the high-k dielectric material can greatly reduce propagation delay and enhance transfer gain and 3-dB bandwidth compared with the conventional pristine MLGNR interconnects. Moreover, it is found that the results obtained by the proposed model have close agreement with Synopsys HSPICE simulation and the maximum relative error for them is less than 5%, and the average efficiency of CPU runtime is improved 95% by using the proposed model, as compared to HSPICE simulation. The proposed design method has many potential applications in improving performance of MLGNR interconnect and providing guidelines for the next generation on-chip interconnect system.