패드 돌기의 기하학적 특성을 고려한 디바이스 패턴의 평탄화 모델링

Abstract

Chemical mechanical planarization (CMP) is a semiconductor process which is necessary for multi-layer interconnection structure. CMP pad is a consumable used in the process and with numerous asperities on the surface that wear out by the load applied from the contact with the wafer. Also, it has a patterned wafer, the step height is gradually removed by contact of the asperities with upper and lower layers. The contact state would be different according to the step height reduction. Likewise, depending on the pattern size at the specific step height, the maximum radius of the asperity curvature differs whether it reaches the down area. In this study, the height distribution of asperities was expressed as a function of time and asperity height taking into account the wear of asperities, and based on the Greenwood-Williamson theory, a mathematical model for material removal rate considering pattern size was derived. The consistency of the novel model is verified with the CMP experiment conducted using oxide patterned wafers, and the experimental data were compared with the residual step height using theoretical removal rate. The root mean square error of the step height reduction was 19.84 nm.