Multichip Module Packaging Research Articles

Multi-Band Power Amplifier Module with Back-Off Efficiency Improvement using Ultra-Compact 3D Vertical Stack Multi-Chip Package for Cellular Handsets.

A highly integrated multi-mode multi-band (MMMB) power amplifier module (PAM) using hybrid bulk complementary metal oxide semiconductor (CMOS), gallium arsenide (GaAs) heterojunction bipolar transistor (HBT), and silicon-on-insulator (SOI) technologies for low band (LB, 824-915 MHz) and high band (HB, 1710-1980 MHz) is proposed. The hybrid MMMB PAM integrates a bulk CMOS controller die, a GaAs HBT power amplifier (PA) die and a SOI switch die on a six-layer laminate. To simultaneously obtain both highly efficient and highly linear characteristics over a wide range of input power levels, a parallel dual-chain PA strategy has been adopted to provide vary bias current and gain for low-power mode (LPM) and high-power mode (HPM) operation. Additionally, a broadband two-section low-pass output matching network design based on the suppression of high-order harmonics is proposed for enhanced efficiency and linearity. In order to achieve further miniaturization, a three-dimensional (3D) die stack multi-chip module (MCM) packaging structure, where the presented CMOS controller die is stacked vertically on the GaAs HBT PA die, is implemented. The measurement results show that the fabricated MMMB PAM achieves 26.1-27 dB of power gains and 38-38.4% of PAEs at an output power (Pout) of 28 dBm in the HPM, and 20.4-20.9 dB of power gains and 12.4-13.8% of PAEs at Pout of 17 dBm in the LPM over LB. For HB, power gains of 24.3-26.7 dB while maintaining PAEs of 38.2-39.9% at Pout of 28 dBm, and power gains of 15.9-17.5 dB while maintaining PAEs of 12.3-12.8% at Pout of 17 dBm are realized in the HPM and LPM, respectively. The fabricated PAM covering five frequency bands and operating at two power modes only occupies a 5 × 3.5 mm2 area. To the best of the authors' knowledge, this work is the first demonstration of a MMMB PAM adopting an ultra-compact 3D vertical stack MCM package with favorable RF performance.

Simba

Package-level integration using multi-chip-modules (MCMs) is a promising approach for building large-scale systems. Compared to a large monolithic die, an MCM combines many smaller chiplets into a larger system, substantially reducing fabrication and design costs. Current MCMs typically only contain a handful of coarse-grained large chiplets due to the high area, performance, and energy overheads associated with inter-chiplet communication. This work investigates and quantifies the costs and benefits of using MCMs with finegrained chiplets for deep learning inference, an application domain with large compute and on-chip storage requirements. To evaluate the approach, we architected, implemented, fabricated, and tested Simba, a 36-chiplet prototype MCM system for deep-learning inference. Each chiplet achieves 4 TOPS peak performance, and the 36-chiplet MCM package achieves up to 128 TOPS and up to 6.1 TOPS/W. The MCM is configurable to support a flexible mapping of DNN layers to the distributed compute and storage units. To mitigate inter-chiplet communication overheads, we introduce three tiling optimizations that improve data locality. These optimizations achieve up to 16% speedup compared to the baseline layer mapping. Our evaluation shows that Simba can process 1988 images/s running ResNet-50 with a batch size of one, delivering an inference latency of 0.50 ms.

Metallization of High Purity Al2O3 Substrate with Autocatalytic NiP Thin Films for Au Interconnections in MCM packaging technology.

A Multichip Module (MCM) is a structure consisting of several ICs (typically bare chips) interconnected on a common supporting substrate and packaged as a single device. In this packaging technology, gold (Au) thin films are used as interconnection tracks terminated by wire bonding process to the chips. Thus, the good quality of theses Au films (for interconnects purpose) is essential. The present work proposes a metallization sequence of high purity (99.9%) and polished Al2O3 substrates, with an autocatalytic (electroless) NiP thin film follow by an electrolytic Au film in order to improve the MCM interconnections quality. The results show NiP and Au films with good adhesion, low roughness, good thickness distribution and optimal electrical properties, which allows us to establish a methodology that guarantees the reproducibility and quality of the Au interconnections in MCM devices.

Thermal Decoupling in Power Electronics Modules Using Thermal Pyrolytic Graphite

Abstract The device within a power electronics module package will fail if the maximum junction temperature is not within the device's permissible maximum temperature rating specified by the manufacturer. Modern electronic miniaturization demands multi-chip module (MCM) packaging providing different semiconductor technology integration, reduced number of component interconnects, and lower power supply. But the huge amount of heat generated by each chip produces thermal coupling among devices, leading to an increase in the junction temperature. The power device specifications in the datasheet assume the devices being mounted on a suitable heatsink. Wide bandgap (WBG) devices like silicon carbide (SiC) devices can generally sustain a maximum junction temperature of about 175 °C – 200 °C. The junction temperature of the WBG devices becomes severe in a high-density high-power module. This highlights the need for a thermal management system to limit the maximum junction temperature within the device's permissible range. As a result, the power module needs to be connected to a heatsink to effectively increase the surface area of the heat dissipation junctions. A high conductivity material based heatsink extracts heat effectively from the module as the thermal resistance value remains low. In this paper, preliminary thermal analysis is done for a high density high-power module where the high in-plane thermal conductivity of thermal pyrolytic graphite (TPG) is exploited in substrate as well as heatsink designs. TPG brings down the junction temperature to a considerably lower level, leading to a safer power module functioning. This paper focuses on the design and proper alignment of the substrate and heatsink with respect to the module layout so that maximum junction temperature is reduced by proper heat extraction far below the operating temperature of the devices and also extent of reduction of the thermal coupling among the power devices placed next to each other on the same plane within the power module.

Gas Ingress and Egress of MEMS Multi-Chip Modules and MEMS Devices

Hermetic microcircuit packaging was the dominant method of protecting semiconductor devices in the 1960s and 1970s. After losing majority market sectors to plastic encapsulated microelectronics over the last a few decades, hermetic packaging remains the preferred method of protecting semiconductor devices for critical applications such as in military, space, and medical fields, where components and systems are required to serve for several decades. MEMS devices impose additional challenges to packaging by requiring specific internal cavity pressures to function properly or deliver the needed quality (Q) factors. In MEMS multichip modules, internal pressure requirement conflicts arise when different MEMS devices require different internal gases and pressures. The authors developed a closed-formed equation to model pressure changes of hermetic enclosures due to gas ingression. This article expands the authors mathematical model to calculate gas pressure of a MEMS multichip module package as well as those of MEMS devices inside the multichip module package. These equations are not only capable of calculating service lifetimes of MEMS devices and multi-chip modules but can also help develop MEMS device packaging strategies to extend the service life of MEMS multi-chip modules.

Implementation of a Temperature Ramp Rate Requirement and Impact on the Packaging Processes

Abstract This paper addresses implementation of a heating and cooling temperature ramp rate requirement and its impact on packaging processes. A complex multi-chip module packaging design includes a printed wiring board, solder attachment of a AlSiC-9 back plate, solder attachment of a multi-room seal frame, soldered surface mount components, power die soldered directly to a heat sink, epoxy attached chip-and-wire die, a welded lid and ribbon cable. Because of complex material interactions that exist in the design, concerns arose about cracking and other thermally induced damage that might occur during temperature excursions. The assembly challenge that resulted was a product requirement to limit the heating and cooling temperature ramp rates during packaging processes. Working together, the design agency and production agency ultimately came to an agreement on what the temperature ramp rate requirement should be and how to qualify the processes and the periodic determination of compliance. The requirement was implemented on all packaging processes that saw a heating and cooling cycle. Epoxy cure after die attach and wire bonding were modified most significantly and are specifically addressed in this paper. Solutions were implemented to minimize impact to assembly flowtime and to minimize the chance of processing errors. Temperature profiles had the ramp rates calculated then documented and qualified based on the process parameters (set point temperatures and dwell times) and the assembly machines, ovens, hot plates and tooling used. Compliance is proved through thermal profiling and calculation of ramp rate. Deviation from the set process will require approval from the design agency.

The visualized investigation of a silicon based built-in heat pipe micropillar wick structure

With the drastically development of the power electronics in the new energy industry, the compact Multi Chip Module packages for the high power density devices became the future tendency. The wick structures inside the flat plate heat pipe, as the key element, have to be fully investigated. The flat plate heat pipe research was toward visualization, micro scaling, multi heat sources, and so on. In here, a thin silicon based plate heat pipe (0.85 mm thick) was constructed with the integrated 250 μm height square micropillar array wick structure. The wick structure was fabricated directly in the silicon substrate (0.35 mm thick) by the dry etching process. Since only 100 μm silicon substrate between the heat resource and the cooling structures, the heat dissipation efficiency could be remarkable strengthen. The silicon microfabrication process is compatible with the standard IC process. This integrated cooling structure could be suitable for many high-power transistor packages. Facilitated with the glass cover transparency, not only the vapor-liquid interfaces could be distinguished, but also the water liquid phase temperature could be measured by the Raman spectral shifting. The Volume of Fluid two-phase flow transient model was established to evaluate the self-adaptability of the micropillar array wick structure. The structure showed a good response for the two heat resources’ power fluctuation. By the nature logarithm linear fitting of the heating power and the heating frequency, the maximum heat dissipation power (21 ± 2 W) of the heat pipe under the stable operation state could be estimated.

Multilayer Millimeter-Wave MCMs [From the Guest Editors' Desk

After a brief review of the state of the art, this focus issue on multilayer millimeter-wave (mmW) multichip modules (MCMs) presents four cover features that showcase the evolution in some key areas of multilayer mmW MCM integration and packaging technologies: advanced interconnects, integration techniques, components, and systems that use additive as well as substructure manufacturing technologies aimed toward making next-generation mmW applications feasible. The first two features provide an overview of state-of-the-art multilayer ceramic-based multichip module and packaging techniques, while the third and fourth features are more specific: one describing SiP eWLB packaging techniques and the other covering recent developments in inkjet and 3-D printed components and subsystems using additive manufacturing technologies.

Design of 240°C Low Voltage Power Supply

Abstract This paper describes various steps followed to design a multi-output low voltage power supply that can operate in a 240°C ambient temperature within a downhole oil exploration tool. The following aspects of the design are considered in detail–circuit topology selection, use of simulation tools to validate the topology, component selection for operation at extreme temperature, component testing and failure analysis, multichip module (MCM) packaging selection, MCM package mounting methodologies, application of thermal stress analysis in circuit layout, reliability assessment and validation testing. This paper provides a step-by-step analysis of the above tasks that must be performed in an iterative manner to achieve a reliable power supply design that can operate at 240°C.

A theoretical study to improve wire sag of ultra-long wire bond loops for 3D/MCM packaging

An innovative theoretical model by altering cross section of gold wire is proposed to reinforce the wire sag stiffness of a wire bond that suffered low yield for the applications of 3-dimensional and multi-chip module (MCM) packaging. The flexural rigidity of a wire bond is found to be a function of the material properties in the moment of inertia of a bond wire. Suffice to say, if the moment of inertia of the bond wire can be raised, the associated sag deflection will be diminished. By manipulating the moment of inertia of the bond wire, the sag deflection of the wire bond can be regulated appropriately to avoid wire sag and even the wire sweep enigma. The ellipse-like cross section of a wire bond is applied as a numerical example to improve the wire sweep stiffness or wire sag stiffness in this study. The results show the sag deflection of a wire bond can be reduced significantly if the ellipse-like cross section is oriented in the preferred direction of flexural rigidity of a wire bond. Furthermore, a systematic study of matching design is performed to control wire sag and wire sweep for the wire bonding applications of overhang cross-stacked and step-stacked packaging. It shows that to use a single diameter of bonding wire in these complicate bonding environments of overhang stacked configurations is a favored possibility. The advantages shown from the theoretical study need to be implemented in further work in a production environment on current wire bonding equipment.

From Chip to Cloud: Optical Interconnects in Engineered Systems

The high-performance server compute landscape is changing. The traditional model of building general-purpose enterprise compute boxes that end-users can configure with storage and networking to assemble their desired compute environments, has evolved to purpose-built systems optimized for specific applications. This tight integration of hardware and software components together with high-density midboard optical modules and an optical backplane allows for unprecedented levels of switching and compute efficiencies and has fueled the penetration of optical interconnects deep “inside the box,” particularly for switch scale-up. We briefly review earlier 40 G/port switching systems based on active optical cables, and present our newest system: An all-optically-interconnected 100 G/port 8.2 Tb/s InfiniBand packet switch ASIC with 41 ports running 100 Gb/s per port interconnected by 12-channel midboard optical transceivers with 25 Gb/s per channel per direction of optical I/O. Using a blind-mate optical backplane, these components enable systems with up to 50 Tb/s bandwidth in a 2U standard rack mount configuration with industry-leading density, efficiency, and latency. For even tighter co-integration of optical interconnects with switch and processor ASICs, we discuss photonic multichip module and interposer packaging technologies that will further improve system energy efficiencies and overcome impending system I/O bottlenecks.

Characterization of High-Power COB LED Module Attached by Low-Temperature Sintered Nanosilver

Along with the increasing demand of high power LED (>1W), multi-chip modules have made great progress to an inevitable trend. Thus, large packaging area is needed to dissipate heat efficiently. In other words, only when we find appropriate packaging materials to control the junction temperature well, can we achieve high-power LED devices in smaller packaging area. Obviously, a die-attach layer as the first-level packaging has a most significant impact on the thermal performance of a power module. So we introduce a novel die-attach material, nanosilver paste, which can be used for connecting multi-chips on the substrate because of its higher melting temperature and better thermal/electrical conductivity than conventional solders and adhesive films. What is more important, because of their ability to emit high brightness, LED packages are being exploited for other systems or fields, and in most cases are exposed to harsher environments. Therefore, the performance and stability of LED packages will be the key to assuring the reliable function of systems. So, in this paper, the optical and electrical properties of the LED device operating under various ambient temperatures from 27 to 120°C were determined. The test results showed that nanosilver paste was a very promising die-attach material in high power multi-chip modules packaging.

Effect of Minute Bends and/or Kinks of Wire Bond Profile on Sag Deflection for 3-D and Multichip Module Semiconductor Packaging

Wire sag and wire sweep developed during encapsulation process are counted for the lower yield rate of chip packaging in semiconductor industry. For conventional packaging, only one single layer of wire bond was constructed along the perimeter of chip system. The issue of wire sag is not a concern until 3-D and multi-chip modules packaging prevails due to the desperate demands of smaller and faster advanced microelectronics devices. Very few researches have been documented on this subject of sag deflection. An empirical equation based upon major profile parameters of a wire bond has been developed by author to predict sag deflection of ellipse shape wire bond. However, the effect of minute bends and/or kinks of wire bond profile on sag deflection has not been included. In this paper, we investigate three frequently used wire bond loops, ${Q}$ loop, ${S}$ loop, and ${M}$ (modified) loop, to look into these minor characteristics of wire bond profile as compared to bond span and bond height. Based on current results, we find that these minute features may dominate the response of sag deflection of a wire bond.

纳米银焊膏封装大功率COB LED模块的性能研究

In order to improve the thermal performance of the high-power LED,the novel nanosilver paste with higher melting temperature and thermal / electrical conductivity was used as die-attach material,and Al2O3-based ceramic substrates were used to form a high-power LED chip-on-board( COB) architecture. To compare the effect of die attach material,high power COB LED modules were packaged by nanosilver paste,traditional Sn / Ag3. 0 / Cu0. 5 solder and silver epoxy,respectively. The photoelectricity properties of three kinds of LEDs under various ambient temperatures from 27 to 120 ℃ were measured to evaluate their thermal management. The accelerated degradation testing under 100 ℃ was measured to evaluate the reliability. The test results show that the nanosilver paste is a very promising die-attach material for high power multi-chip modules packaging.

Effects of Die-Attach Material and Ambient Temperature on Properties of High-Power COB Blue LED Module

With the increasing demand of high-power light-emitting diode (LED), multichip modules have made great progress. A die-attach layer as the first-level packaging has a most significant impact on the thermal performance of a power module. In this paper, we introduce a novel die-attach material, nano silver paste, which can be used for connecting multichips on the substrate. This nano silver paste has a higher melting temperature and thermal/electrical conductivity than the conventional Sn3Ag0.5Cu solders and silver epoxy films. In addition, Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ceramic substrates were used to form a high-power LED chip-on-board architecture because of their high thermal conductivity and low coefficient of thermal expansion. Recently, because of their ability to emit high brightness, LED packages are being exploited for the automotive, aircraft, space exploration, nuclear industries, and in most cases are exposed to harsh environments. Therefore, the performance and stability of LED packages will be the key to assuring the reliability of LED modules. In this paper, the properties of the LED modules bonded separately with nano silver, Sn3Ag0.5Cu, and silver epoxy and operating under various ambient temperatures from 27°C to 100°C were determined. The test results showed that the nano silver paste is a very promising die-attach material for high-power multichip modules packaging.

Thermal Analysis of MCM Packaging

This paper describes the use of infra-red thermography for the thermal study in the development stage of custom enclosures for multi-chip modules. Some limitations of conventional thermographic measurements are discussed and an approach for enhancing its application to quality control and diagnostics of faulty multi-chip module packages is proposed. The results from thermal measurements of radio-frequency range multi-chip module prototype in an open and a closed Quad Flat No Lead package are presented. DOI: http://dx.doi.org/10.5755/j01.eee.20.5.7110

Fabrication of a microstrip patch antenna integrated in low-resistance silicon wafer using a BCB dielectric

This paper demonstrates a technique for microstrip patch antenna fabrication using a benzocyclobutene (BCB) dielectric. The most distinctive feature of this method is that the antenna is integrated on a low-resistance silicon wafer, and is fully compatible with the microwave multi-chip module packaging process. Low-permittivity dielectric BCB with excellent thermal and mechanical stability is employed to enhance the performance of the antenna. The as-fabricated antenna is characterized, and the experimental results show that the antenna resonates at 14.9 GHz with a 1.67% impedance bandwidth.

Highly integrated CMOS RF SPDT switch with ESD and unit cell optimisation in MCM

Presented is the performance of a highly integrated RF single-pole double-throw (SPDT) switch fabricated in a 0.18 µm bulk CMOS process and housed in a low-cost laminated multi-chip module (MCM-L) package. A switch controller is also implemented and consumes ∼40 µA from a 3.4 V supply. The switch, based upon the 1.8 V thin-oxide devices with resistive body-floating and unit cell layout optimisation techniques, achieves an insertion loss of 0.52/0.78 dB at 0.9/2.45 GHz, respectively. TX-to-RX isolation of > 29 dB and return loss of > 15 dB are achieved at these frequencies. The measured IP1dB of 21.7/21.2 dBm and IIP3 of 38.3/37.4 dBm are accomplished at 0.9/2.45 GHz, respectively. Finally, the switch achieves a RF electrostatic discharge (ESD) rating of 4 kV for the ± 2 kV human body model and 500 V for the ± 200 V machine model.

Robust Design Analysis on Fatigue Life of Lead-Free Sn0.5Ag Solder in a Multichip Module Package

System-in-package (SiP) has become a mainstream technology in IC package industry as it provides the solutions to the growing needs of high speed functions, mobility/portability, energy efficiency, and miniaturization of electronic products. One special form of SiP is the multi-chip module (MCM) in which multiple integrated circuits (ICs), semiconductor dies or other discrete components are packaged onto a unifying substrate. Thus, the reliability of package integrity becomes one of the major reliability concerns. In the present paper, a robust design analysis on the thermo-mechanical reliability of an MCM package with flip-chip technology is demonstrated. Our results show that for the specific package, the CTE of the substrate is the most influential factor to the fatigue reliability of the package. The optimal combination of the parameters is recommended. The robust design analysis optimizes the fatigue life from 165 cycles to 1080 cycles which is a 554.5% gain on the fatigue life.

Measurement and Analysis of a High-Speed TSV Channel

Using high-speed through-silicon via (TSV) channels is a potential means of utilizing 3-D interconnections to realize considerable high-bandwidth throughput in vertically stacked and laterally distributed integrated circuits. However, although the TSV and a silicon interposer in a high-speed TSV channel lead to a significant decrease of the interconnect length, the received digital signal after transmission through a TSV channel is still degraded at a high data-rate due to the nonidealities of the channel. Therefore, an analysis of the signal integrity in a high-speed TSV channel is necessary. In this paper, a single-ended high-speed TSV channel is measured and analyzed in the frequency-domain and the time-domain. To measure the high-speed TSV channel, two types of test vehicles are fabricated, consisting of TSVs and interposers. With these test vehicles, the channel losses are measured in the frequency-domain up to 20 GHz, and eye-diagrams are measured in the time-domain at 1 Gb/s and 10 Gb/s. Based on these measurements, the channel loss, characteristic impedance, and reflection of the high-speed TSV channel are analyzed and compared to those of the channel in multichip module (MCM) package. Because of the losses from the silicon-substrate and the thin oxide-layer used in the TSVs, the overall loss of the high-speed TSV channel is higher than that of the MCM channel. In addition, the characteristic impedance of the high-speed TSV channel is frequency-dependent, whereas that of the MCM channel is frequency-independent. Moreover, in contrast to the MCM channel, the reflection is negligible in the high-speed TSV channel because the channel is too short and the losses are too high to be affected by the reflection. Finally, the design guidance of a high-speed TSV channel for wide bandwidth is determined based on the analysis of the measurements.