Multi-stage Noise Research Articles

High Spectral Efficient Free-Space Optical Communication Using Multi-Stage Noise Shaping Delta-Sigma Modulation With Partial Transmit Sequence Algorithm and Arithmetic Coding

High Spectral Efficient Free-Space Optical Communication Using Multi-Stage Noise Shaping Delta-Sigma Modulation With Partial Transmit Sequence Algorithm and Arithmetic Coding

Incipient Bearing Fault Extraction based on an Adaptive Multi-stage Noise Reduction Method

Considering the strong nonlinear and non-stationary characteristics of rolling bearing vibration signals, this paper proposes a multi-stage noise reduction method using adaptive variational mode decomposition and modulation signal bispectrum (AVMD-MSB) to extract the fault features of rolling bearings. Firstly, the AVMD is employed to adaptively select VMD parameters K and α and decompose the signal into a series of Intrinsic mode functions (IMFs), which allows an adaptive selection of the parameters of VMD. Then, all IMF components are reconstructed with weights according to the index of correlation kurtosis to avoid accidental omission of the IMFs containing important fault information. Finally, MSB is implemented to further suppress residual noises and interference components in the signal, precisely extract the bearing fault features. Numerical simulation and case study show that the AVMD-MSB is more advantageous in extracting fault characteristics from rolling bearing vibration signals compared with AVMD-Envelope and conventional VMD-MSB.

Optimized MASH-SR Divider Controller for Fractional-N Frequency Synthesizers

The divider controller in a conventional phase-locked loop fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> frequency synthesizer modulates the instantaneous division ratio of the feedback divider. The divider controller is typically a digital circuit that performs quantization of its input signal. Multi-stage noise shaping digital delta-sigma modulators (MASH DDSMs) and successive requantizer (SRs) are two representative divider controller architectures offering lower complexity and better spur performance, respectively. The MASH-SR, as a hybrid of these two classes of divider controllers, can achieve both lower hardware cost than the SR and better performance against spurs than a MASH DDSM. In this work, we present an optimized MASH-SR hybrid and compare the design with its conventional MASH DDSM and SR counterparts.

A New Noise Shaping Approach for Sigma-Delta Modulators Using Two-Stage Feed-Forward Delays and Hybrid MASH-EFM

Sigma-delta modulators use a noise-shaping technique to curtail the noise power in the band of interest during digital-to-analog conversion. Error feedback modulator employs an efficient noise transfer function for time varying inputs than any other sigma-delta modulators. However, the efficiency of the conventional noise transfer function degrades and the quantizer saturation issue provokes when the input signal reaches to full scale. This work proposes a new noise transfer function which is a combination of transfer functions of two-stage Feed-forward delays and a novel Hybrid multi-stage noise shaping-error feedback sigma-delta modulator. The noise transfer function of two-stage Feed-forward delays mitigates the concern of quantizer saturation. The noise transfer function offered by the Hybrid multi-stage noise shaping-error feedback architecture provides sustainable solutions to limit cycles and idle tones. The simulation concludes that the proposed noise-shaping approach obtains comparatively high signal-to-quantization noise ratio than the conventional error feedback modulators. Other performance parameters like spurious-free dynamic range, effective number of bits and signal-to-noise plus distortion ratio are also significantly improved.

Noisy Supervised Deep Learning for Remote Sensing Image Segmentation Using Electronic Maps

Deep learning has made substantial progress in remote sensing image segmentation tasks. It usually requires a large number of high-quality annotation maps (i.e., clean labels), which are labor-intensive. In this paper, we propose to use abundant electronic maps (i.e., noisy labels) to supplement a small number of clean labels to solve the problem of massive label production. In addition, we propose a multi-stage noise supervised framework (NSDI) to prevent noise from deteriorating the performance of deep model. NSDI consists of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">clean training</i> , <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">weight initialization</i> , and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">hybrid training</i> stages. In the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">clean training</i> stage, we train a segmentation model using a small amount of clean labels and remote sensing images to compute the confusion probability matrix. In the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">weight initialization</i> stage, we use the confusion probability matrix as well as the prediction probability to calculate the label reliability of the electronic map. In the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">hybrid training</i> stage, an adaptive weighted loss function based on cross-entropy is used to dynamically update the label reliability. Then we train model further using electronic maps with the support of the adaptive weighted loss function and label reliability. Experiments were undertaken on 2,656 images of 512 × 512 pixels. Ablation studies show that NSDI improves the model robustness as well as the segmentation quality.

Correlated Dual-Loop Sturdy MASH Continuous-Time Delta-Sigma Modulators

This article presents a new multi-loop delta-sigma modulator (DSM) structure that combines the advantages of both the traditional multi-stage noise shaping (MASH) and sturdy MASH (SMASH) architectures. It removes the need for an explicit quantization error extraction digital-to-analog converter (DAC) typically required in multi-loop structures, which allows to eliminate the delay mismatch problem related to the intrinsic propagation delay of the first loop quantizer. The proposed architecture essentially uses the SMASH architecture as its core and has similar characteristics. However, it further simplifies the structure allowing to remove all the feedback DACs in the cascaded loop. The prototype DSM fabricated in a 65-nm process achieves signal-to-noise-and-distortion ratio (SNDR) and dynamic range (DR) of 73.4 and 78.3 dB, respectively, in an 18.75-MHz bandwidth. With 1.1/1.5-V (1.5 V for DAC) supply voltage, the prototype DSM consumes 17.85 mW at 600-MHz operating speed corresponding to a Walden and Schreier figure of merits (FOMs) of 124.1 fJ/conv-step and 168.6 dB (using DR result), respectively.

A low power MASH digital delta-sigma modulator with accurate output average value

This paper presents a modified Multi-stAge noise Shaping (MASH) digital delta-sigma modulator (DDSM). The proposed structure has an accurate mean value and efficient randomization for all input values to reduce the spurious tones. In addition, the proposed MASH based Sigma Delta modulator has less hardware complexity and power consumption compared to conventional structures. The Verilog HDL-based simulations and experimental implementation on FPGA have been used to verify the randomization efficiency of the proposed structure. Power consumption and hardware complexity are verified by post-synthesis simulations. The randomization efficiency of the proposed MASH DDSM is also verified by phase noise simulation of the fractional- N frequency synthesizer.

A 7.2–27.3 GHz CMOS LNA With 3.51 ±0.21 dB Noise Figure Using Multistage Noise Matching Technique

A wideband low-noise amplifier (LNA) with low and flat noise figure (NF) is presented in this article. For conventional wideband noise matching, the noise performance in the high-frequency region of the entire wideband is usually deteriorated due to the frequency-dependent nature of the minimum noise figure (NF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> ) for a MOSFET. To address this issue, a novel wideband noise matching approach aiming at noise matching in high band is proposed. This approach can reduce the NF in high band at the cost of a slight NF increase in low band, eventually achieving a low and flat NF and thus a better overall noise performance for a wideband LNA. In addition, the multistage noise matching technique is employed at high frequencies to further reduce the NF caused by the second amplification stage. To validate the proposed techniques, a two-stage LNA prototype was designed and fabricated using a 65 nm CMOS process. The experimental results indicate a peak gain of 16.6 dB with a −3 dB bandwidth (BW) from 7.2 to 27.3 GHz (a fractional BW of 116%). Within the entire band of interest, the simulated NF is low and almost constant (3.3–3.4 dB), while the measured NF falls within the range of 3.30–3.72 dB. Considering the uncertainty of NF measurement, a 0.21 dB NF flatness is one of the best results among the reported millimeter-wave wideband LNAs. The measured third-order input intercept point (IIP3) is −6 dBm at 20 GHz, while the power consumption is 13.2 mW. In addition, only two passive transformers are used in this design, leading to a compact chip core area (0.14 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ).

Multistage noise reduction processing for vibration signal of hydropower units

In actual field testing environments of hydropower units, unit vibration signals are often contaminated with noise. In order to obtain the real vibration signal, a multi-stage vibration signal denoise method SG-SVD-VMD is proposed for the guide bearing nonlinear and non-stationary vibration signals. And the root mean square error (RMSE) and signal to noise ratio (SNR) are used to evaluate the noise reduction ability of eight methods. The results show that the noise-canceling ability of this proposed method has improved to some extent. It can effectively suppress the noise of the hydropower units vibration signals. This method can effectively identify the shaft track and the running state of hydropower units.

Design and Simulation of A Third Order MASH (1-2) Modulator for GSM Applications

This paper presents a design and simulation of proposed MASH (Multi-stAge noiSe sHaping) modulator which can be used for GSM applications. MASH technique is chosen for GSM system, since low settling time, spurious level and phase noise can be obtained by using this technique. The phase noise obtained with this modulator is 30 dB if compared with other modulating techniques. Matlab (R2013a) is used for simulation of 3rd order, 32-bit digital MASH modulator.

Spur Immunity in MASH-Based Fractional-N CP-PLLs With Polynomial Nonlinearities

Spurious tones appear in the output phase noise spectrum of a fractional-N frequency synthesizer when nonlinearities are present in the loop. These spurs are generated by the interaction between the nonlinearity and the quantization error that the digital Σ modulator (DDSM) introduces into the system. This paper analyzes the spurious effect of polynomial nonlinearities on fractional-N CP-PLLs equipped with multi-stage noise shaping (MASH) DDSMs of different orders. This leads to a proof of immunity from spurs for PLLs based on higher order MASH modulators in the case of certain polynomial nonlinearities.

Noise Cancellation in Computed Tomography Images through Adaptive Multi-Stage Noise Removal Paradigm

Image de-noising is a noise removal approach, which is utilized to remove noise from the noisy image and is utilized to protect the significant features of images namely, corners, edges, textures, and sharp structures. For medical diagnosis Computer tomography (CT) images are mainly utilized. Due to acquisition and transmission in CT imaging, the noise that appears leads to poor image quality. To overcome this problem, an efficient Noise cancellation in computed tomography images using adaptive multi-stage noise removal paradigm is proposed. The proposed approach consists of three phases namely, Optimal Discrete Wavelet Transform, first stage noise removal using Block Matching, and 3D filtering (BM3D) filter and second stage noise removal using the bilateral filter (BF). Initially, Discrete Wavelet Transform (DWT) is applied to the input image to diminish noise in CT images. In this method, co-efficient ranges are optimally selected with the help of Crow Search Optimization (CSO) algorithm. Secondly, to remove the noise present in the bands, BM3D algorithm is applied. Finally, bilateral filter is applied to the BM3D output image to further enhance the image. The performance of the proposed methodology is analyzed in terms of Peak signal-to-noise ratio (PSNR), Root Mean Square Error (RMSE), and Structural Similarity Index (SSIM). Furthermore, the multi-stage noise removal model obtained gives the best PSNR values compared to other techniques.

A Time-Domain 147fsrms 2.5-MHz Bandwidth Two-Step Flash-MASH 1-1-1 Time-to-Digital Converter With Third-Order Noise-Shaping and Mismatch Correction

A 50 MS/s two-step flash-MASH 1-1-1 time-to-digital converter (TDC) employing a two-channel time-interleaved time-domain register with an implicit adder/subtractor realizes an error-feedback topology. Such an error-feedback unit of 1st-order noise-shaping TDC can be cascaded as a multi-stage noise shaping (MASH) configuration to achieve higher-order noise-shaping and, thereby high resolution. This paper also discusses different noise sources, linearity and noise tradeoffs in noise-shaping TDC and then demonstrates a histogram testing technique to correct the mismatch of 1st stage flash TDC. An on/off-chip delay modulation (DM) measurement technique is presented to characterize the TDC linearity and noise performance. Fabricated in 40-nm CMOS technology, the proposed TDC consumes 1.32 mW from a 1.1 V supply. At frequency below 2.5 MHz, the TDC error integrates to 147fsrms, which is equal to equivalent flash resolution of 1.6 ps.

Mitigation of “Horn Spurs” in a MASH-Based Fractional-N CP-PLL

A Fractional-N Charge Pump (CP) PLL with a Multi-stAge noise SHaping (MASH) 1-1-1 divider controller has been reported to exhibit pairs of spurious tones called “horn spurs”. The phenomenon has been confirmed in measurements on a commercial wideband synthesizer. This brief presents an analysis of the phenomenon and techniques to mitigate it. MATLAB simulation results are presented for a type-II CP-PLL with a third order MASH Digital $\Delta \Sigma $ Modulator (DDSM) to validate the techniques that are shown. Measurement results are also presented.

A Low-Spur MASH Delta-Sigma Modulator With an Adaptive Length Extension Technique

This brief presents a novel multistage noise–shaping (MASH) delta-sigma modulator that has low spurs for all input values by the proposed adaptive length extension technique. Based on the feedforward structure, the accumulators in the proposed MASH are fully utilized to realize an adaptive feedforward gain to compensate for the sequence length loss due to input. The proposed MASH can extend the output sequence length to the maximum under any input, thus to reduce spurs. Simulation results show that the quantization noise of the proposed MASH is distributed widely with no noticeable spurs. Synthesized with 180nm CMOS technology, the increase in hardware cost of the proposed MASH is slight.

Influence of Initial Condition on Wandering Spur Pattern in a MASH-Based Fractional-N Frequency Synthesizer

A Multi-stAge noiSe sHaping Digital Delta-Sigma Modulator (MASH DDSM) is commonly employed as the divider controller in a fractional-N frequency synthesizer. Previous work has considered a time-varying pattern of spurious tones, called wandering spurs, which originate in the DDSM. Two cases have been considered, namely when the fractional part of the division ratio is (i) close to zero or (ii) close to a simple fraction. In both cases, the wandering spur pattern is independent of the initial state of the modulator. This brief considers a third case where the pattern of wandering spurs depends explicitly on the initial state. The phenomenon is explained analytically and simulation results are presented. Theoretical predictions are confirmed with spectral measurements from a representative commercial monolithic fractional-N frequency synthesizer.

Analysis of Wandering Spur Patterns in a Fractional-$N$ Frequency Synthesizer With a MASH-Based Divider Controller

The Multi-stAge noise SHaping Digital Delta-Sigma Modulator (MASH DDSM), which is commonly used as a divider controller in a fractional- $N$ frequency synthesizer, can produce a time-varying periodic pattern of tones in the output spectrum of the synthesizer; these are known as wandering spurs. In this work, a detailed analysis of the cause of wandering spur patterns in a MASH 1-1-1 DDSM-based fractional- $N$ frequency synthesizer, supported by experimental measurements, is presented.

A Highly Linear OTA-Less 1-1 MASH VCO-Based $\Delta\Sigma$ ADC With an Efficient Phase Quantization Noise Extraction Technique

In this article, an efficient technique is introduced to extract the quantization noise of a multi-phase voltage-controlled oscillator (VCO)-based quantizer (VCOQ) in the time domain as a pulsewidth modulated (PWM) signal. Using this technique, a new highly linear VCO-based 1-1 multi-stage noise shaping (MASH) delta–sigma analog-to-digital converter (ADC) structure is presented. This architecture does not require any operational transconductance amplifier (OTA)-based analog integrators or power-hungry linearization methods. The first stage is a closed-loop multi-phase VCO-based voltage-to-phase (V-to-P) converter, and the second stage is an open-loop multi-phase VCO-based voltage-to-frequency (V-to-F) converter. Using the proposed technique, the phase quantization error of the first stage is extracted as a pulse signal and then fed to the second stage. The input of the first VCO is a very small amplitude signal, and the input of the second VCO is a two-level PWM signal. Therefore, the VCO non-linearity does not limit the overall ADC performance, mitigating the need for power-hungry linearization methods. The prototype achieves second-order noise shaping with a DR/SFDR/SNR/SNDR of 82.7/88.7/80.3/79.7 dB for an input signal BW of 2 MHz. The fabricated design consumes 1.248 mW from a 0.9-V supply.

MASH DDSM with Negative Feedback

This paper proposes a Multi-stAge noise SHaping (MASH) digital delta-sigma modulator (DDSM) with negative feedback to acquire the maximum sequence length. The mathematical analysis shows that the sequence length is [Formula: see text], which is not affected by the input values and initial conditions, where [Formula: see text] is the smallest prime number above the quantization interval [Formula: see text], and [Formula: see text] is the order of the MASH DDSM. Moreover, the influence of the negative feedback on the input range is analyzed. Finally, the simulations and experiments are performed to verify the theoretical analysis.

A 5-MHz bandwidth 78.1-dB SNDR 2-2 MASH delta-sigma modulator

ABSTRACTThis paper presents a 4-bit, 2–2 multi-stage noise shaping (MASH) delta-sigma modulator (DSM) fabricated using a 0.18 µm complementary metal oxide semiconductor (CMOS) process. The DSM was designed using a cascade-of-integrators with a feedforward (CIFF) structure. The first integrator was designed to reduce the loading effect of the system’s front-end circuit using a switched-resistor integrator instead of the conventional switched-capacitor method. The CIFF structure requires an active adder, which is generally implemented with a high-bandwidth high-swing amplifier. In this paper, the active adder is eliminated and an adder-less integrator is implemented in the MASH DSM. The DSM prototype has an over-sampling ratio (OSR) of 16 and a 160 MHz sampling frequency. The prototype’s measured signal-to-noise ratio (SNR) is 82.4 dB and the signal-to-noise-plus-distortion ratio (SNDR) is 78.1 dB for a signal bandwidth of 5 MHz. The measured total power consumption is 26 mW at a 1.8 V supply voltage, and the chip core size is 0.67 mm2. The energy required per conversion step is 0.4 pJ/conv.