Multi-stage Circuit Research Articles

Phase noise of signal generators with multichannel digital synthesizers

Wide use of a direct digital synthesizer (DDS) and digital to analog converters (DAC) in digital antenna arrays permits for fast modulation parameters variations and beam positioning, and also improves the quality of beam forming due to high accuracy of signal generation. However, any systematic and random phase deviations of array channels not only lead to distortion of radiation pattern but also cause deterioration of signal processing at receiver end. Phase noise is one of critical parameters of such systems. Traditional theory and empirical methods assumes small or zero phase deviation of phase of channel output signal when combining these signals. We have proposed the model in which coupling of AM and PM noise persists for any arbitrary phase deviation of channels in multistage circuits comprising multichannel digital synthesizers. Absolute phase noise measurements of combined DACs outputs for zero phase offset and antiphase modes with two values of DAC output signal amplitude difference permit for estimation of residual phase noise of DAC and clock receiving and distribution circuitry and demonstrate good compliance of results of calculation.

Improved Marx Pulse Generator With Auxiliary Trigger Topology (2022)

Marx multi-stage circuits based on avalanche transistors are widely used in high-power nanosecond pulse applications. In response to the low reliability of the conventional Marx circuit, this paper analyzed the corresponding failure mechanism and discovered that the conduction modes were the main cause of failure. Based on this, a new topology is designed, by changing the conduction mode from "overvoltage switching-on" to "triggering switching-on". The simulation and measurement results show that the new structure has the advantages of high efficiency, stable operation, low output delay and short output pulse front. Meanwhile, to further improve the output efficiency,= a multiplexed stacking solution is designed based on the new structure, and the simulation results show that the output efficiency is up to 95%. The research in this paper can provide solutions for accurate and reliable synchronous triggering of key units such as gas switches in pulsed power systems, and also provide references for the design of high-efficiency nanosecond pulse generators.

Line Surge Arresters Applications On The Multi Circuit Overhead Lines

This paper presents application of line surge arresters (LSA) on the different voltage level multi circuit overhead lines. Double circuit shielded compact line with and without distribution circuit on the same tower is analyzed. Distribution circuit has lower insulation level, meaning that almost all flashovers will happen on that circuit. Flashovers on the distribution circuit help to improve lightning performance of the transmission circuits. Flashovers on the distribution circuit diverts fraction of the lightning current along its phase conductors, improving at the same time coupling between distribution and transmission circuits. All software simulations are performed using sigma slp software package. A short description of the modeling for multi circuit flashover rate determination is given. In order to prevent flashovers on the distribution circuit LSA are installed on this circuit only. The improvement in the transmission circuit lightning performance is similar to that obtained without LSA. LSA installed on the distribution circuit are much cheaper than transmission LSA.

Mitigation of common mode failures at multi-circuit line configurations by application of line arresters against back-flashovers

Due to the limited number of corridors multi circuit line configurations are often applied. These overhead lines frequently consist of high towers that are subject to lightning strokes. In case of higher current amplitudes and higher footing resistances due to bad earthing conditions back-flashovers are caused leading to common mode failures and to severe outages. The paper describes investigations performed by means of computer simulations to identify the towers of a multi-circuit line consisting of voltage levels 380 kV, 220 kV and 110 kV that are endangered by back-flashovers of the 110-kV double-circuit lines. The footing resistance of towers of the targeted line section has been measured by an instrument at high-frequency. Influence of various factors on the back-flashover over 110 kV insulator strings has been studied by means of EMTP-ATP simulations. Different current waveforms of the lightning stroke have been used to represent the first stroke and subsequent strokes. The towers are represented by the models described in [3], [8]. Available flashover analysis methods [7], [8], [12], [13] like leader development method by Pigini et al and by Motoyama, and voltage-time integration method by Kind have been applied. The towers at which back-flashover is more likely to occur than at other towers are identified by the time integral of voltage according to Kind. Various factors like tower footing impedance, tower surge impedance and tower height are considered. Application of line a surge arrester is shown to be a successful mitigation technique to reduce the back-flashover rate of those 110 kV lines. The lightning overvoltage performance of surge arresters has been analyzed by means of digital simulations. Based on the results of investigations line arresters were installed on the towers in question. Since the installation no further common mode failure has been observed.

Analyzing Scaled Reduced Precision Redundancy for Error Mitigation Under Proton Irradiation

Reduced precision redundancy (RPR) is an alternative to triple modular redundancy (TMR) that reduces the area overhead at the expense of minor accuracy loss in case of error. In this work, we propose a Scaled RPR approach for multistage circuits and analyze the error mitigation tradeoffs. As a case study, several fast Fourier transform designs were tested with low-energy protons and fault injection. Experimental results show that the proposed approach achieves error mitigation with good accuracy, while significantly reducing the area overhead with respect to a full precision TMR approach.

220 GHz Multi Circuit Integrated Front End Based on Solid‐State Circuits for High Speed Communication System

This paper presents the research on a 220 GHz multi circuit inte-grated front end based on solid-state circuits. This integrated front end integrates a 220 GHz subharmonic mixer, a 110 GHz tripler, a 110 GHz 8 dB hybrid coupler and a 220 GHz waveguide bandpass filter (BPF) in one single block. Compared to the traditional transceivers which usually use cascade connection of the independent mixers and multipliers, the size of the proposed multi circuit integrated front-end block is 25 mm × 20 mm × 20 mm, ten times smaller than the cascading transceiver. In order to check the tripler’s output power, a modified compact 110 GHz 8 dB hybrid coupler is set between mixer and tripler. Due to the characteristics of the hybrid coupler, the deterioration of cascading transceiver’s performance caused by mismatch has also been improved. In addition, to achieve single sideband (SSB) communication, a 220 GHz BPF with high selectivity is integrated in the circuit. The measured conversion loss of the fabricated multi circuit integrated front end is less than 11 dB, where the LO and RF frequency are 37 and 210−220 GHz. Based on this front-end, a 220 GHz high speed communication system has been setup and it can achieve 10 Gbps data transmission using 16QAM modulation.

Long-Range Detection of a Wirelessly Powered Resistive Transducer.

Wireless measurement of resistance variation is particularly desirable inside confined cavities where wire connection and battery replacement are undesirable. Compared to capacitive or inductive transducers, resistive transducers have better availability, whose resistance changes can be directly converted into detectable voltages by electric bridges. However, to wirelessly operate electric bridges on batteryless platforms, multistage circuits are required to convert dc signals into wireless signals, making the whole system hard to miniaturize without using complicated integrated circuits. Alternatively, resistive transducers can be incorporated into passive resonators for contactless characterization by the backscattering method. This design, however, is ineffective beyond the near field, and it requires complicated line shape analysis of resonators' frequency response curves. Here, we will significantly improve the remote detectability of a resistive transducer, by inductively coupling it with a parametric resonator. Upon activation by wireless pumping power with an external antenna, the parametric resonator can self-oscillate and emit strong oscillation signals. The temperature-induced resistance change is converted into linear frequency shifts of the oscillation signal that can be detected over large distance separations for up to 20-fold the sensor's own dimension. Every 0.1 °C of temperature change can be converted into 8 kHz of frequency shift that is approximately threefold larger than the linewidth of oscillation peak. This sensor maintains good linearity between 25 °C and 41 °C, providing enough range for physiological monitoring. In conclusion, we have fabricated a resistance-to-frequency converter for remote detection of resistance changes via a wirelessly powered parametric oscillator. Besides this proof-of-concept demonstration for temperature sensing, the general concept of resistance-to-frequency conversion will improve the remote detectability of a broad range of resistive transducers for physiological and environmental monitoring.

Lightning protection performance of quadruple-circuit 500 kV transmission lines on the same tower with composite cross arm

In recent years, composite materials cross-arm (CMCA) towers have been gradually used in 10 kV, 35 kV or other transmission lines with lower voltage level in China. However, it is rarely used in higher voltage level transmission lines, especially in multi circuit lines on the same tower. Because of its higher height, we should pay more attention to the lightning protection performance of high voltage level multi circuit lines on the same tower. In this work, the simulation and calculation analysis of Lightning stroke model of quadruple-circuit 500 kV transmission line is done to compare CMCA tower with steel tower. The research shows that the tolerance lightning level of CMCA tower is superior to conventional steel tower, The lightning withstand level of single circuit flashover is 45% higher than that of steel tower and the minimum shielding failure lightning withstand level is 47% higher than that of steel tower. The data can provide the theoretical basis for the construction and optimization design of high voltage CMCA tower.

Fine-Grain Reconfigurable Logic Circuits for Adaptive and Secure Computing via Work-Function Engineered Schottky Barrier FinFETs

A comprehensive simulation study has been conducted to show fine-grain reconfigurability in CMOS circuits using work-function engineering (WFE) on Schottky Barrier (SB) FinFETs for sub-10nm gate length. The study has three subsections. First, two-transistor (2T) & 4T AOI (and-or-invert)/ OAI (or-and-invert) gates with select bits that allow multiple logic functions are introduced. Secondly, the use of WFE to create ultra-compact reconfigurable logic circuits of fundamental operations (0,1,OR, AND,NAND,NOR,XOR) are explored via novel 2T, 3T and 4T gates. These circuits include one or two select bits that are capable of commanding up to four functions with two inputs. To further illustrate the potential of WFE for reconfigurable logic, novel multi-stage circuits such as compact full-adders are also modelled via TCAD simulations. Power×delay product (PDP) figures and DC gain of the proposed gates are quantified and compared against the CMOS designs with similar functionality. Finally, we also design a novel compact one-bit arithmetic logic unit (ALU) which has seven exclusive logic operations (1, NAND, OR, XOR, NOR, Addition, Subtraction) with three select bits using only 26 SB-FinFETs, saving substantial amount of power and chip area. The trade-offs between the number of metal work-functions used in the designs, circuit complexity and simulated performance metrics are also provided. The comparative simulations between reconfigurable SB-FinFET based designs versus conventional p-n junction FinFET circuits show that WFE can lead to absolutely minimalist reconfigurable CMOS logic blocks using ×3 to ×10 less power and between ×2 and ×15 less area than static CMOS counterparts. Although they suffer greater delays (×2 to ×5), the overall PDP performance remains comparable to conventional CMOS.

Application of Multi-Stage Window Comparator Circuit with Safety Mode for Swell Voltage Control in Low Voltage Systems

Application of Multi-Stage Window Comparator Circuit with Safety Mode for Swell Voltage Control in Low Voltage Systems

CMOS-Like Logic Circuits With Unipolar Thin-Film Transistors on Flexible Substrate

In this article, the feasibility of CMOS-like logic circuits has been demonstrated on a flexible substrate with only n-type TFTs. Here, a 1-to-2 decoder was realized by bootstrapped inverters and NAND gates. Theoretical analysis and simulation results show low static leakage current and full output-swing features. The effect of applied mechanical strain that causes circuit performance variations is also presented. The decoder is capable of driving the rows of a Quarter-VGA display panel with 60-Hz refresh rate. Experimental results show that the decoder can perform a continuous 48-h crosstalk-free operation under tensile or compressive bending situations, thus proving the effectiveness of bootstrapped logic gates in forming complex multistage digital circuits.

Wireless Powered Encoding and Broadcasting of Frequency Modulated Detection Signals.

Wireless transmission of locally detected RF signals is necessary for long-term operation of batteryless and embedded transducers. To improve signal transmission efficiency over larger distances, multi-stage circuits were employed to down-convert RF signals before encoding them onto the emitted carrier wave. Such multi-stage arrangement had complicated design and high-power consumption. Here, a compact and low-power wireless modulator is introduced to directly encode input RF signals onto its oscillation carrier wave. The modulator consists of a double frequency parametric resonator that is overlaid with a single frequency passive resonator to create three resonance modes. By properly adjusting the substrate thickness between resonators, the highest resonance frequency is tuned to approximately the sum of lower two resonance frequencies, enabling efficient conversion of wireless pumping power into sustained oscillation currents. When an input RF signal is present with a certain frequency offset, the oscillation signal can be frequency modulated by the input signal to create multiple modulation sidebands separated by the offset frequency. The frequency encoded carrier wave can transmit MRI signals over larger distance separations to maintain constant image sensitivity, making the modulator useful to improve the remote detectability of miniaturized implantable and interventional devices.

Lossy Signal-Interference Filters and Applications

Lossy signal-interference transversal filtering sections (TFSs) composed of two in-parallel transmission-line segments with input-output matching lines-reflective-type part-and open-ended stubs with input resistors-lossy part-are presented. First, in their bandstop and dual-band bandpass versions, this class of lossy TFS is applied to the design of filtering networks with input-/two-port-quasi-reflectionless (QR) stopbands, such as wide-band bandstop filters (BSFs) and dual-band bandpass filters (BPFs). Furthermore, multistage circuit architectures made up of equal and dissimilar lossy TFSs for higher rejection and broader stopband realization, respectively, and higher selectivity dual-band BPF synthesis are described. Subsequently, in its bandpass counterpart, the conceived approach of lossy TFS is exploited to develop single-/multistage sharp-rejection bandpass filters (BPFs) with a flattened transmission band. The operational foundations of the engineered types of lossy TFSs for the suggested applications and theoretical design examples are provided. In addition, for experimental-validation purposes, four microstrip filter prototypes are manufactured and characterized, as follows: 2-GHz two-stage symmetrical QR BSFs with similar and frequency-contiguous bandstop TFSs for higher rejection and broader stopband shaping, respectively, a 1.4/2.6-GHz input-QR dual-band bandpass TFS, and a 2-GHz five-stage lossy BPF with enhanced passband amplitude flatness and spectrally enlarged attenuated bands.

Hybrid Logical Effort for Hybrid Logic Style Full Adders in Multistage Structures

One of the critical issues in the advancement of very large scale of integration circuit design is the estimation of timing behavior of the arithmetic circuits. The concept of logical effort provides a proficient approach to comprehend and assess the timing behavior of circuits with conventional CMOS (C-CMOS) structure. However, this technique is not working for circuits with a hybrid structure. On the other hand, numerous circuits with the hybrid structure which are faster and consume less power than C-CMOS one have been proposed for different applications such as portable and IoT devices. In this regard, the necessity of having and use of a simple and efficient timing behavior method like conventional logical effort for analysis of the hybrid adder circuits is inevitable. This paper proposes an efficient analysis and modeling technique that enables designers to assess the timing behavior of hybrid full adder circuits at the block level and anticipate their performance in multistage circuits. The gain and selection factor are introduced as a criterion for accurate selection and optimization of the hybrid adder cells measurable on the single test bench for management of energy efficiency and performance tradeoff. The proposed method is investigated using 32-nm CMOS and FinFET technologies.

Linear Circuit Analysis: a Tool for Addressing Challenges and Identifying Opportunities in Process Circuit Design

One of the most important processing engineering tools for designing mineral processing facilities is linear circuit analysis. This technique, originally conceived and developed by Meloy, Williams, and Fuerstenau nearly four decades ago, provides fundamental insights regarding how unit operations interact and respond when arranged in multi-stage processing circuits. Researchers have successfully utilized this tool to improve the operating performance of industrial processing circuits incorporating coal spirals, magnetic separators, mineral spirals, and eddy current separators. More recently, advanced versions of this tool have also been developed to provide a standardized framework for circuit mass balance calculations, to output exact analytical solutions to mass yield and value-based efficiency expressions, and to estimate uncertainty propagation in separation circuits. This article reviews the historical development of linear circuit analysis, describes how the technique has evolved to address more complex circuit design problems, and presents industrial case studies that highlight the importance of this process engineering tool.

Use of the Lorenz Cycle in Heat Pumps

The use of the Lorenz cycle together with the inverse Carnot cycle increases the conversion efficiency of a heat pump by 25–30%. The Lorenz cycle may be implemented either through the use of nonazeatropic substances or by multistage circuits. The Lorenz cycle is more efficient at low temperature differences of the working substances.

Research on Safety Protection for Live Working on 1000kV AC Transmission Line with AC and DC Multi-circuit Transmission Lines

In recent years, in order to save line corridors and reduce the scope of demolition, some new transmission modes for high voltage AC and DC power transmission line are proposed. According to the characteristics of the parallel transmission line, this paper studies the distribution characteristics of the electric field intensity of multi circuit parallel transmission lines and the single circuit transmission line. Comparing and analysing the simulation results of the electric field strength, the safety measures for live working of 1000kV AC transmission line with multi circuit parallel transmission lines is put forward. That is the electric field protective equipment and measures used in the live line work of the 1000kV UHV AC single circuit line can meet the requirements of the live operation of the 1000kV UHV AC double circuit line.

Research on safety protection for live working on ±800kV DC transmission line with AC and DC multi-circuit transmission lines

In recent years, in order to save line corridors and reduce the scope of demolition, some new transmission modes for high voltage AC and DC power transmission line are proposed. According to the characteristics of the parallel transmission line, this paper studies the distribution characteristics of the electric field intensity of multi circuit parallel transmission lines and the single circuit transmission line. Comparing and analysing the simulation results of the electric field strength, the safety measures for live working of ±800kV DC transmission line with multi circuit parallel transmission lines is put forward. That is the electric field protective equipment and measures used in the live line work of the ±800kV UHDC single circuit line can meet the requirements of the live operation of the ±800kV UHDC multi-circuit transmission line.

Multifinger MOSFETs’ Optimization Considering Stress and INWE in Static CMOS Circuits

Strain engineering and inverse narrow width effect (INWE) are among the main causes of layout-dependent variations in narrow width devices. Transistor sizing and layout without considering these effects at a prelayout stage may result in suboptimal design and design/layout iterations. In this paper, we model the channel stress variations in multifinger gate structure (MFGS) empirically using 3-D technology computer aided design simulations. Thereafter, we use these stress models along with a model for INWE to establish a physics-based relationship between effective drive current and number of fingers in MFGS. We also design single-stage combinational standard cells and predict the values of their logical effort using our approach. The performance of the standard cells using our approach improves significantly compared with the conventional approach. Inverter chains (buffers) are representative and extensively used multistage circuits. Using our model of effective drive current, we propose a methodology to optimize the buffer designed and layout to maximize performance in stress-enabled technologies. We observe that the proposed methodology results in a significant reduction in power dissipation up to 35% and reduction in silicon area up to 43% as compared with the existing methodologies.

Atypical Voltage Transitions in FinFET Multistage Circuits: Origin and Significance

For optimizing FinFET circuit-level parameters (such as number of fins) with performance predictability, it is necessary to understand the nature of voltage transitions at the nodes of a multistage logic circuit. Since the device’s extension region parasitics are strong, these transitions need to be studied while considering them. We find using Technology Computer aided design simulations that the transitions at the input/output nodes of FinFET inverter chain stages are unconventional in nature for an important range of fan-out loads and input transition time values. The transition has three parts. First, a monotonous increase/decrease, followed by a duration of slowly varying voltage (which we call drag), and again followed by a monotonous increase/decrease. The duration of this drag is a strong function of a circuit’s transistor sizing (number of fins). We explain this phenomenon to be due to the strong gate-controlled modulation of carrier densities in the low-doped part of the drain extension region. We demonstrate that this phenomenon has serious implications on circuit delay and power consumption.