Atypical Voltage Transitions in FinFET Multistage Circuits: Origin and Significance

Abstract

For optimizing FinFET circuit-level parameters (such as number of fins) with performance predictability, it is necessary to understand the nature of voltage transitions at the nodes of a multistage logic circuit. Since the device’s extension region parasitics are strong, these transitions need to be studied while considering them. We find using Technology Computer aided design simulations that the transitions at the input/output nodes of FinFET inverter chain stages are unconventional in nature for an important range of fan-out loads and input transition time values. The transition has three parts. First, a monotonous increase/decrease, followed by a duration of slowly varying voltage (which we call drag), and again followed by a monotonous increase/decrease. The duration of this drag is a strong function of a circuit’s transistor sizing (number of fins). We explain this phenomenon to be due to the strong gate-controlled modulation of carrier densities in the low-doped part of the drain extension region. We demonstrate that this phenomenon has serious implications on circuit delay and power consumption.