Design of low delay low power hybrid logic based flip-flop using FinFET

Abstract

The need for a low-power and high-speed technology for computation of digital signals is rising due to the fast growth of technological innovations. Flip-flops serve as fundamental elements in signal processing technologies. Hybrid logic has great potential for constructing flip-flop circuits because of its minimal transistor count as well as low-power properties.The present investigation presents a design for a tiny and low-power hybrid flip-flop that operates fully statically. The design has been developed by utilizing different circuitry-reduction techniques. It incorporates a hybrid logic approach combining pass transistor logic to decrease circuit complexity. The ongoing work utilizes a hybrid logic with low delay and low power to generate flip-flops. The proposed flip-flop design significantly decreases latency compared to the existing master-slave flip-flops. This flip-flop remains immune to clock overloading, resulting in reduced power consumption. Reducing the quantity of PFET (P-channel Field Effect Transistor) transistors enhances the circuit's delay, area, and power consumption. Implementing these circuit optimization techniques yields several benefits, such as reduced CLOCK-to-OUT and DIN-to-OUT node delays, decreased average power consumption, lower leakage power, and a transistor count of only 18. The results were achieved using Cadence Virtuoso at 18 nm finFET technology, with varied process corners, supply voltages ranging from 0.7 V to 1 V, and temperatures ranging from -50 °C to 75 °C. This study also presents a Monte Carlo simulation of power consumption, leakage, and delay for the suggested flip-flop. According to the simulations, the recommended flip-flop exhibits exceptional stability. The recommended flip-flop has lower power usage by at least 17.95 % compared to standard architectures due to the lower number of PFET transistors.