A methodology for NBTI circuit reliability at reduced power consumption using dual supply voltage

Abstract

Actually there is a great interest of new methodologies for reducing the power consumption of integrated circuits. Power consumption raises the operating temperature that devices experience. Consequently, circuit reliability is affected due to temperature-dependent mechanisms like Negative Bias Temperature Instability (NBTI). This paper proposes a methodology based on dual supply voltage technique to mitigate delay degradation due to NBTI for applications requiring to reduce the power consumption. In the proposed methodology, the low voltage supply is slightly lower than the high (nominal) voltage supply. Therefore, voltage level converters are not required. A gate metric is proposed to estimate the benefit of lowering the supply voltage of a gate on circuit power consumption and delay degradation. The results show that NBTI-induced delay degradation and power consumption are reduced at some small delay penalty. This leads to circuits with lower power consumption and higher reliability.