Reliability Aware Gate Sizing Combating NBTI and Oxide Breakdown

Abstract

Negative Bias Temperature Instability (NBTI) and Oxide Breakdown (OBD) are two key reliability concerns for nanometer VLSI circuits. Gate over-sizing has been done in the past to mitigate the effect of NBTI and aging to meet performance constraints. However, this could make the entire circuit more prone to OBD. In this paper, we propose a new gate sizing formulation that considers both NBTI-induced delay degradation and OBD-induced circuit lifetime. Since NBTI and OBD are highly sensitive to the input vectors in a conflicting way, we consider their dependencies on signal probabilities. Moreover, we take into account the degradation in rise slew due to NBTI which could affect the fall delay/slew of the inverting gates in the next stage, and this has not been considered in previous work on NBTI aware gate sizing. Experimental results on industry strength benchmarks demonstrate that by incorporating OBD into holistic gate sizing, we can achieve more reliable circuit without compromising the circuit performance and area.