Multi-phase Clock Research Articles

A High-Temperature, Low-Noise Readout ASIC for MEMS-Based Accelerometers.

This paper presents the development and measurement results of a complementary metal oxide semiconductor (CMOS) readout application-specific integrated circuit (ASIC) for bulk-silicon microelectromechanical system (MEMS) accelerometers. The proposed ASIC converts the capacitance difference of the MEMS sensor into an analog voltage signal and outputs the analog signal with a buffer. The ASIC includes a switched-capacitor analog front-end (AFE) circuit, a low-noise voltage reference generator, and a multi-phase clock generator. The correlated double sampling technique was used in the AFE circuits to minimize the low-frequency noise of the ASIC. A programmable capacitor array was implemented to compensate for the capacitance offset of the MEMS sensor. The ASIC was developed with a 0.18 μm CMOS process. The test results show that the output noise floor of the low-noise amplifier was −150 dBV/√Hz at 100 Hz and 175 °C, and the sensitivity of the AFE was 750 mV/pF at 175 °C. The output noise floor of the voltage reference at 175 °C was −133 dBV/√Hz at 10 Hz and −152 dBV/√Hz at 100 Hz.

Charge controlled delay element enabled widely linear power efficient MPCG‐MDLL in 1.2V, 65nm CMOS

SummaryIn this work, a robust, low‐power, widely linear multiphase clock generation and multiplying delay‐locked loop (MPCG‐MDLL) architecture is realized, using a new differential charge‐mode delay element circuit topology. The heart of any MPCG‐MDLL architecture is the delay element, and hence, the characteristics of the delay element influence the overall performance of the MPCG‐MDLL, in terms of its specifications such as peak‐to‐peak jitter, lock range, delay range, control voltage range, and power consumption. The proposed eight‐phase MPCG‐MDLL along with the charge‐mode delay element outperforms the conventional MPCG‐MDLLs that deploy delay elements such as a current‐starved inverter (CSI), wide‐range CSI, triply controlled delay cell, digital‐controlled delay element, and the like. The eight‐phase MPCG‐MDLL along with the new charge‐mode delay element circuit topology is implemented in 1.2‐V, 65‐nm CMOS technology. The performance results show that the eight‐stage delay line has a delay range from 640 to 960 ps over the rail‐to‐rail control voltage range. The implemented MPCG‐DLL is robust over process, voltage, and temperature (PVT) corners and exhibits a lock range of 400 MHz and a peak‐to‐peak jitter of less than 60 fs for all the DLL output phases and peak‐to‐peak jitter of 0.54 and 1.24 ps for the synthesized 5‐GHz clocks for an input reference clock frequency of 1.25 GHz. The MPCG‐MDLL consumes 4.74 mW of power and occupies an area of 0.017 mm2.

A Wide Dynamic Range and Low Bit Error Pixel TDC Suitable for Array Application

This brief presents a cascade pseudo 3-level time-to-digital converter (TDC) based on wideband phase-locked loops (PLLs) for photon time of flight measurement. In each pixel, a 9-bit pseudo random synchronous counter composed of linear feedback shift register is served as a high-level coarse TDC. Its counting clock is directly coming from the synchronous counter served as the middle-level TDC. The low-level fine TDC is based on time-interpolation technology and directly use the low-jitter multi-phase clock signal generated by the PLL to complete the fine quantization of the residue time. In addition, proper timing control and error suppression methods are implemented in the proposed TDC. The circuit is demonstrated in TSMC 0.35- ${\mu }\text{m}$ CMOS process. Under the condition of 10-MHz input reference frequency and 3.3-V supply voltage, the wideband PLL can be locked from 146 to 450 MHz. The resolution of the TDC will change from 856 to 278 ps. At 450 MHz, the measured DNL around $15\boldsymbol {\mu }\text{s}$ is–0.1 to 0.1 LSB and the INL is–0.05 to 0.2 LSB.

A 10-Gb/s Eye-Opening Monitor Circuit for Receiver Equalizer Adaptations in 65-nm CMOS

A 10-Gb/s on-chip 1-D eye-opening monitor (EOM) for receiver front-end equalizer boost gain adaptations is presented. The proposed EOM circuits report in real-time horizontal eye-openings using equalizer output by calculating the probability density of the waveform in the central row of pixels of the eye diagram. In addition, a novel multi-phase generator circuit with a delay gain calibration is also demonstrated. It is suitable for EOM circuits to generate a multi-phase sampling clock. The proposed 1-D-EOM circuit is included in a 10-Gb/s receiver design to verify its adaptation functions, and the circuit is implemented using the 65-nm CMOS technology. The sampling phase resolution is 1.5625 ps (where the time for one bit is 100 ps, with a total of 64 phases), and the response time is $64~\mu \text{s}$ . The total power consumption of the EOM circuit is 1.5 mW with a 1-V supply voltage, and the circuit occupies a layout area of 60 $\mu \text{m}\,\,\times $ 450 $\mu \text{m}$ . The results show that the reported horizontal eye-opening value is proportional to the value from a real eye diagram monitor from the test buffer.

Low-latency adiabatic superconductor logic using delay-line clocking

Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic family. The switching energy of an AQFP gate can be arbitrarily reduced via adiabatic switching. However, AQFP logic has somewhat long latency due to the multiphase clocking scheme, in which each logic operation requires a quarter clock cycle. The latency in AQFP logic should be improved in order to design complex digital circuits such as microprocessors. In the present paper, we propose a low-latency clocking scheme for AQFP logic, which we call delay-line clocking. In delay-line clocking, the latency for each logic operation is determined by the propagation delay of the excitation current, which can be much shorter than a quarter clock cycle. Our numerical simulation shows that AQFP gates can operate with a latency of only a few picoseconds. We fabricated an AQFP circuit adopting delay-line clocking using the 10 kA/cm2 Nb high-speed standard process provided by the National Institute of Advanced Industrial Science and Technology. The circuit was demonstrated at 4 GHz with a latency of 10 ps per gate. The above results indicate that delay-line clocking can significantly reduce the latency in AQFP logic.

Synchronous Circuit Design With Beyond-CMOS Magnetoelectric Spin–Orbit Devices Toward 100-mV Logic

The supply voltage scaling has become increasingly challenging in the advanced CMOS technology due to the threshold voltage requirement for transistor OFF leakage, limiting the system energy efficiency. Spintronic logic utilizes the physical quantity of magnetization or spin as a computation variable, offering new design paradigms in terms of ultralow voltage operation and nonvolatility, but suffering from switching inefficiency of the charge-to-spin conversion. The magnetoelectric spin–orbit (MESO) device has been proposed as a new alternative logic device candidate to solve these issues by magnetoelectric transduction using a novel multiferroic oxide [both ferroelectric (FE) and antiferromagnetic], a ferromagnet and a spin injection layer. It enables a path toward 10–100 $\times $ switching energy reduction compared to CMOS inverter in 2018 node, due to the device and material innovations of a novel switching mechanism. In this paper, in order to build a MESO logic family for new circuit and architecture exploration, we propose for the first time the fundamental building blocks such as MESO sequential and combinatorial circuits for the synchronous logic operation. We employ a transistor sharing and a novel multiphase clocking scheme to address the circuit design issues such as clock control, directionality of state propagation, and power gating and enable the design exploration for MESO digital logic. Based on the proposed circuit techniques, we demonstrate these MESO logic functions operating at a supply voltage of 100 mV and a clock period of 1.2 ns with 320-ac FE polarization through the circuit simulations.

A Second-Order Noise-Shaping SAR ADC With Passive Integrator and Tri-Level Voting

This paper presents a low-power and scaling-friendly noise-shaping (NS) SAR ADC. Instead of using operational transconductance amplifiers that are power hungry and scaling unfriendly, the proposed architecture uses passive switches and capacitors to perform residue integration and realizes the path gains via transistor size ratios inside a multi-path dynamic comparator. The overall architecture is simple and robust. Since the noise transfer function is set by component ratios, it is insensitive to process, voltage, and temperature (PVT) variations. Besides the proposed architecture, this paper also presents two new circuit techniques. A tri-level voting scheme is proposed to reduce the comparator noise. It outperforms the majority voting technique by exploiting more information in the comparator output statistics and providing an extra decision level. A dynamic multi-phase clock generator is also proposed to guarantee non-overlapping and support an arbitrary number of phases. A prototype 9-bit NS-SAR ADC is fabricated in a 40-nm CMOS process. It consumes $143~\mu \text{W}$ at 1.1 V while operating at 8.4 MS/s. Taking advantage of the second-order NS, it achieves a peak SNDR of 78.4 dB over a bandwidth of 262 kHz at the oversampling ratio of 16, leading to an SNDR-based Schreier figure of merit (FoM) of 171 dB.

A 40-nm CMOS 7-b 32-GS/s SAR ADC With Background Channel Mismatch Calibration

This brief presents a 7-b 32-GS/s successive approximation register analog-to-digital converter (ADC) using a massive time-interleaving (TI) architecture. For low-skew multi-phase clocks, generation utilizing a delay-locked loop (DLL) phase-detector (PD) with a reduced offset is proposed to minimize skew between the clocks. Different clock path delays caused by distributed sub-ADCs over a large area in a massive TI-ADC are compensated for by multiplexing master clocks from the DLL. Offsets and skews in the sub-channels are calibrated on chip in the background via an additional dedicated sub-channel. A prototype chip was implemented in a 40-nm CMOS process with an active area of 0.36 mm2. The measured SFDR and SNDR of the prototype ADC at a conversion rate of 32 GS/s are 43.1 and 31.4 dB, respectively. The ADC, including the input buffers, consumes 125 mW under a single 0.9-V supply.

Fast-Transient-Response Low-Voltage Integrated, Interleaved DC–DC Converter for Implantable Devices

A new self-start-up switched-capacitor charge pump is proposed for low-power, low-voltage and battery-less implantable applications. To minimize output voltage ripple and improve transient response, interleaving regulation technique is applied to a multi-stage Cross-Coupled Charge Pump (CCCP) circuit. It splits the power flow in a time-sequenced manner. Three cases of study are designed and investigated with body-biasing technique by auxiliary transistors: Four-stage Two-Branch CCCP (TBCCCP), the two-cell four-stage Interleaved Two-Branch CCCP (ITBCCCP2) and four-cell four-stage Interleaved Two-Branch CCCP (ITBCCCP4). Multi-phase nonoverlap clock generator circuit with body-biasing technique is also proposed which can operate at voltages as low as CCCP circuits. The proposed circuits are designed with input voltage as low as 300 to 400[Formula: see text]mV and 20[Formula: see text]MHz clock frequency for 1[Formula: see text]pF load capacitance. Among the three designs, ITBCCCP4 has the lowest ramp-up time (41.6% faster), output voltage ripple (29% less) and power consumption (19% less). The Figure-Of-Merit (FOM) of ITBCCCP4 is the highest value among two others. For 400[Formula: see text]mV input voltage, ITBCCCP4 has a 98.3% pumping efficiency within 11.6[Formula: see text][Formula: see text]s, while having a maximum voltage ripple of 0.1% and a power consumption as low as 2.7[Formula: see text]nW. The FOM is 0.66 for this circuit. The designed circuits are implemented in 180-nm standard CMOS technology with an effective chip area of [Formula: see text][Formula: see text][Formula: see text]m for TBCCCP, [Formula: see text][Formula: see text][Formula: see text]m for ITBCCCP2 and [Formula: see text][Formula: see text][Formula: see text]m for ITBCCCP4.

On-Chip Static Phase Difference Measurement Circuit With Gain and Offset Calibration

A gain and offset-calibrated 3-state phase detector is proposed to accurately measure static phase difference. Forcing the phase detector to operate in two different modes provides the full-scalegain since the sum of the two results is ${2}{\pi }$ . Flipping the inputs and averaging the results cancels the offset. Proposed circuit enhancements realize a robust reset and a gain, independent of waveform rise/fall times. A $0.13-\boldsymbol {\mu }\text{m}$ CMOS prototype of the proposed enhanced phase detector has errors ≤ 0.5° for 2.4-GHz quadrature inputs. It consumes 3.6mA from 1.2V and occupies 0.0416 mm2. The proposed circuit can be used for on-chip measurement and calibration of multi-phase clock generators in radios and clocking circuits.

A 1-<inline-formula> <tex-math notation="LaTeX">$\mu$ </tex-math> </inline-formula>s Ramp Time 12-bit Column-Parallel Flash TDC-Interpolated Single-Slope ADC With Digital Delay-Element Calibration

This work presents a hybrid column-parallel time-to-digital-converter interpolated (TDC) single-slope (SS) ADC with a digital delay element feedback. The proposed scheme solves the multiphase clock period matching problem in flash TDC-interpolation of SS ADCs without the use of a delay-locked-loop. The architecture employs open-loop delay elements for multiphase clock generation forming a lowered TDC radix of $1024\times128$ linescan image sensor testchip manufactured in a 0.13- $\mu \text{m}$ 1P3M CMOS process. The ADC operates at 250 MHz and achieves a 1- $\mu \text{s}$ ramp time and 4.4- $\mu \text{s}$ digital correlated double sampling row time for a 12-bit linear A/D conversion.

Analysis, Calibration, and Performance Evaluation of a Generalized <inline-formula> <tex-math notation="LaTeX">$N$ </tex-math> </inline-formula>-Phase Quadrature Phase Shift Frequency Selective Receiver

In this paper, a new low-power and blocker-tolerant receiver architecture, the generalized N-phase quadrature phase shift frequency selective (QPS-FS), is proposed and analyzed that is suitable for radio frequency (RF) energy harvesting networks. A complete comparative analysis of the N-phase QPS-FS receiver with conventional N-path passive mixer (P-M) receiver is also provided. The QPS-FS receiver utilizes the impedance translation concept to improve the receiver selectivity but eliminates the need of an active multiphase clock generation circuit used in the conventional N-path P-M receivers. It uses a single clock signal source at the desired signal carrier frequency and a phase shift network in the RF path of the receiver for frequency downconversion and quadrature (I/Q) demodulation. The QPS-FS receiver requires a slower clock signal source, the frequency of which is equal to the desired band RF signal carrier frequency ( $f_{c})$ as opposed to at least N/2 times $f_{c}$ for the conventional N-path P-M receivers. Consequently, the lower frequency clock source requirement extends the frequency coverage of the receiver by a factor of at least N/2 for a given clock source with a fixed maximum frequency. Reduction of the operating frequency and elimination of the active multiphase clock generation circuit would also eventually reduce the overall power consumption for the whole receiver system as confirmed through measurements. A wideband receiver calibration approach provides less than 2% of error vector magnitudes between the transmitted and received constellation points for various modulated signals having bandwidths up to 4 MHz.

An Odd Phase CDR With Phase Interpolator Trimming

This brief presents an odd phase Bang–Bang phase detector-based CDR architecture that has a unique property that the clock phases sampling the data automatically become aligned to the center of the data. This eliminates both the residual phase error of the quadrature correction and the quadrature corrector loop itself. An adaptive closed loop weight trimming algorithm is proposed to suppress the non-linearity of phase interpolator (PI). With this algorithm, very high PI linearity is achieved. Additionally, the resulting linearity is maintained over process, voltage, temp. (PVT). A compensation method for the phase offsets of the multiphase clock going into the PI is proposed. Phase offset compensation reuses the same sensing block, which is used for PI trimming. After settling, a phase alignment error of of ≤ 1.7° is achieved. At 2.67-GHz clock frequency, the PI trimming achieves DNL ≤ 0.45 LSB and INL ≤ 0.43 LSB across PVT. The phase offsets to PI input are corrected to within ±2.5% of the ideal phase spacing.

A programmbale 8-channel multiphase clock generator with 360 phases for focus ultrasound applications

An area efficient, programmable multichannel, multiphase clock generator is proposed to improve the phase resolution for focus ultrasound applications. By using the proposed phase-folding method, the cell amount for generating 360 phases are reduced from 360 to 38 cells. The proposed clock generator is able to provide 360 phases in real-time with 1° phase resolution, 1–51.9% 6-bit DPWM for each channel, and which output frequency varies from 0.1 to 1.5 MHz. Due to the proposed multiphase system is a real-time system, many independent multichannel applications such as focus ultrasound could easily adopt the proposed structure. A new phase-error calibration method for PLL is also present in this paper for reducing the static phase-error due to process voltage and temperature variation. It improves the accuracy of the phase difference in the multiphase system. The proposed ASIC was fabricated in a standard 0.18 μm CMOS process. Measured result shows that multiphase clock generator is able to provide 360 selective phases for each channel. The derived DNL is from −0.106 to +0.108 LSB, and the INL is from −0.284 to +0.449 LSB at 1 MHz.

Components of Artificial Neural Networks Realized in CMOS Technology to be Used in Intelligent Sensors in Wireless Sensor Networks.

The article presents novel hardware solutions for new intelligent sensors that can be used in wireless sensor networks (WSN). A substantial reduction of the amount of data sent by the sensor to the base station in the WSN may extend the possible sensor working time. Miniature integrated artificial neural networks (ANN) applied directly in the sensor can take over the analysis of data collected from the environment, thus reducing amount of data sent over the RF communication block. A prototype specialized chip with components of the ANN was designed in the CMOS 130 nm technology. An adaptation mechanism and a programmable multi-phase clock generator—components of the ANN—are described in more detail. Both simulation and measurement results of selected blocks are presented to demonstrate the correctness of the design.

A Low Overhead, Within-a-Cycle Adaptive Clock Stretching Circuit With Wide Operating Range in 40-nm CMOS

Adaptive voltage frequency scaling (AVFS) techniques based on in-situ timing monitoring can mitigate the excessive timing margin caused by process, voltage and temperature (PVT) variations. However, they usually adjust the frequency by clock gating, clock half-division, or phase locked loop configuration, which cause large performance loss or need a long lock time. Thus, a compact structured adaptive clock stretching circuit is proposed here for very rapid frequency adjustment. It is very useful for AVFS systems by stretching the clock cycle with only within-a-cycle response time. The proposed architecture generates multi-phase clocks through a series of delay elements and continuously picks an appropriate phase clock to form a stretched clock. It also uses a process voltage temperature monitor to adjust the phase clock selection and makes this circuit suitable under PVT variations. Fabricated in 40-nm CMOS process, it only occupies a core area of 85* <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$83~{\mu }\text{m}^{2}$ </tex-math></inline-formula> . Measurements show that it can stretch the clock cycle immediately upon the stretch signal with within-a-cycle response time. It has a wide voltage range from 0.43 V to 1.1 V, with power consumptions of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$38.2~{\mu }\text{W}$ </tex-math></inline-formula> at 0.43 V/10 MHz and 4.55 mW at 1.1 V/1.2 GHz. Plus, it can provide configurable stretch amounts for the AVFS system. Thus, it can provide a within-a-cycle, low overhead frequency adjustment solution for AVFS systems.

A 6.7–11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS

A single-loop referenceless clock and data recovery (CDR) with a compact frequency acquisition scheme is presented. A bang–bang phase–frequency detector (BBPFD) is proposed that tracks the frequency difference by detecting the drift direction of the non-return to zero bit stream with respect to the multi-phase clock and generates UP/DN output signals accordingly. When frequency locked, the BBPFD is degenerated into the conventional bang–bang phase detector (BBPD). The UP/DN output signals from the BBPFD are thus connected directly to the loop filter, thereby reducing the acquisition time without any loss of cycles. The effect of sampling phase mismatch is analyzed, and the capture range is calculated. In addition, the frequency acquisition time is analytically derived and verified by simulation. The proposed CDR has been implemented in a 65-nm CMOS process and occupies an active area of 0.047 mm2. The measured capture range is 6.7–11.2 Gb/s, and the frequency acquisition time is less than 2.19 $\mu \text{s}$ . The proposed CDR achieves error-free operation (BER < 10−12) for PRBS31 pattern and consumes 22.5 mW at 10 Gb/s.

A standard-blocker tolerant receiver front-end using noise-canceling LNA with passive N-path filter and variable pulse-width multi-phase clock generator

In this paper, input impedance characteristics of N-path filters is used to reject standard blockers at the input port of a receiver front-end. Due to using variable capacitors in the multiphase LO generator, the results of each performance parameter of the design shows a slight change in value at the whole of frequency range. The receiver NF is about 2.45 dB at 1 GHz switching frequency. The proposed receiver front-end is analyzed and is simulated at the schematic level using CMOS 90 nm technology with a 1.5 V supply voltage.

A Multi-Phase Coupled Oscillator Using Inductive Resonant Coupling and Modified Dual-Tank Techniques

This paper presents a novel coupled oscillator RFIC for multi-phase clock generation. The design achieves low phase noise while maintaining strong coupling among oscillator cores. The proposed transformer-based dual-tank topology forms a loop of coupling path for enhanced multi-phase coupling. To facilitate strong magnetic coupling among oscillator cores, the proposed transformers utilize resonant inductive coupling to enhance the voltage swing at the coupled wing. The phase noise optimization is accomplished by leveraging the adaptive biasing feedback and the enhanced dual-tank technique. The behavioral model based on Alder’s equation as well as the analysis of the tank response is given. Full electromagnetic (EM) modeling involving all transformers and the passive interconnecting routes has been performed using the EMX software in order to ensure that simulated performance reflects measurement environment. The prototype RFIC of the proposed circuit with eight phases is implemented in a 65-nm CMOS radio frequency (RF) silicon on insulator technology. The measured phase noise is −124.3 dBc/Hz at 1-MHz offset from 2.41 GHz with 7-mW power consumption per core, and the operating frequency can be digitally tuned from 1.81 to 2.41 GHz. The phase noise can be further improved to −128.2 dBc/Hz at 1-MHz offset from 2.41 GHz by increasing the power consumption to 15 mW per core.

A 12-Gb/s HDMI 2.1 quarter-rate transmitter in 28-nm bulk CMOS process

A four-lane 12-Gb/s per lane high-definition multimedia interface (HDMI) 2.1 transmitter is developed in 28-nm bulk CMOS process. To relieve the burden of the generation and distribution of clock, quarter-rate architecture is employed where the duty-cycle and phase spacing errors of multi-phase clock are automatically corrected by analog–digital converter based digital logic. The output driver terminated with 3.3-V supply is implemented only with 1.8- and 1.0-V transistors which are protected from over-voltage stress by double-cascoding with adaptive bias generation. The 4-lane HDMI 2.1 transmitter consumes 12.0-mW/lane at 12-Gb/s and occupies 0.12-mm2 active area.