A 6.7–11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS

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A single-loop referenceless clock and data recovery (CDR) with a compact frequency acquisition scheme is presented. A bang–bang phase–frequency detector (BBPFD) is proposed that tracks the frequency difference by detecting the drift direction of the non-return to zero bit stream with respect to the multi-phase clock and generates UP/DN output signals accordingly. When frequency locked, the BBPFD is degenerated into the conventional bang–bang phase detector (BBPD). The UP/DN output signals from the BBPFD are thus connected directly to the loop filter, thereby reducing the acquisition time without any loss of cycles. The effect of sampling phase mismatch is analyzed, and the capture range is calculated. In addition, the frequency acquisition time is analytically derived and verified by simulation. The proposed CDR has been implemented in a 65-nm CMOS process and occupies an active area of 0.047 mm2. The measured capture range is 6.7–11.2 Gb/s, and the frequency acquisition time is less than 2.19 $\mu \text{s}$ . The proposed CDR achieves error-free operation (BER < 10−12) for PRBS31 pattern and consumes 22.5 mW at 10 Gb/s.