Multi-operand Adders Research Articles

Retraction Note to: A novel cognitive Wallace compressor based multi operand adders in CNN architecture for FPGA

Retraction Note to: A novel cognitive Wallace compressor based multi operand adders in CNN architecture for FPGA

A Delay Efficient Hybrid Parallel Prefix Variable Latency CSKA Based Multi-Operand Adder with Optimized 5:2 Compressor and Skip Logic

In this paper, a delay efficient multi-operand adder (MOA) is introduced by considering the compression logic and variable latency carry skip adder (VL-CSKA). Here, an optimized 5:2 compressor is initially used to increase the speed of MOA by reducing the number of operands before giving as input to VL-CSKA. Also, the VL-CSKA is modified by replacing the carry propagation with complementary complex gates (CCG) and nucleus stage with improved parallel prefix structure for increasing the speed with fewer components. The delay, area, power, and logic depth of the proposed hybrid parallel prefix VL-CSKA (HPP-VL-CSKA) is also reduced by modifying the group Propagate-Generate (PG) logic in the parallel prefix structure. Also, a new circuit for XOR/XNOR gate is used for the reduction of the delay and power consumption significantly. The synthesis result shows that the suggested adder design overtakes the existing adders by consuming only 5953 area, 1.763power, 1.251fJ and 3516.63 ADP for 20 number of operands, each with 32 bit inputs.

Development of a device for multiplying numbers by means of FPGA

The authors propose the description of the development of a device for multiplying numbers. The device for multiplying numbers on the field-programmable gate array (FPGA) includes two input and one output registers, fifty-six single-digit adders, sixty four logic elements AND, one exclusive OR gate. The main scientific and technical task in developing a device for multiplying numbers is to reduce hardware complexity using single-bit adders and logic elements. Introduction includes description of works of scientists and researchers whose publications are devoted to design and development of multiplier construction methods, multiplier FIR performance improvement by right-shift and addition method on FPGA (field-programmable gate array) basis. The implementation of MAC-block, hardware implementation of binary multiplier on the basis of multi operand adder, multiplier design by right-sliding and addition with control automaton in the FPGA basis is the actual research tasks presented in a number of papers. The description of features of multiplier implementation, high-speed multipliers with variable bit rate, studies of approaches for designing modular multipliers, FPGA image processing using Brown multiplier for performing convolution operation find application in problems of performance and speed. Also, a number of authors describe implementation of conveyorization method, design of dual multiplier, construction method of 8-bit multiplier with reduced delay, 8-bit high-density systolic multiplier arrays on FPGA and development of high-performance 8-bit multiplier using McCMOS technology. A fragment of a developed device for multiplying numbers is presented in the work by the authors. The principle of operation of a device for multiplication is described. The description of connected elements of the device is given. The timing diagrams of operation of a device for multiplication of numbers are presented.

WITHDRAWN: A faster approach to add Multi operands using unified pipelining technique

The article presents novel multi operand adder using seamless pipelining concept. The proposed adder synthesized using Xilinx 14.2 software and implemented on Virtex-5(xc5vfx30t-3ff665) device. Delay and device utilization parameter i.e. number of slice LUTs are compared with carry propagate adder (CPA), carry save adder (CSA), and conventional pipelined adder. And it shows our method gives the highest frequency of operation among all the methods.

Numerical behavior of NVIDIA tensor cores.

We explore the floating-point arithmetic implemented in the NVIDIA tensor cores, which are hardware accelerators for mixed-precision matrix multiplication available on the Volta, Turing, and Ampere microarchitectures. Using Volta V100, Turing T4, and Ampere A100 graphics cards, we determine what precision is used for the intermediate results, whether subnormal numbers are supported, what rounding mode is used, in which order the operations underlying the matrix multiplication are performed, and whether partial sums are normalized. These aspects are not documented by NVIDIA, and we gain insight by running carefully designed numerical experiments on these hardware units. Knowing the answers to these questions is important if one wishes to: (1) accurately simulate NVIDIA tensor cores on conventional hardware; (2) understand the differences between results produced by code that utilizes tensor cores and code that uses only IEEE 754-compliant arithmetic operations; and (3) build custom hardware whose behavior matches that of NVIDIA tensor cores. As part of this work we provide a test suite that can be easily adapted to test newer versions of the NVIDIA tensor cores as well as similar accelerators from other vendors, as they become available. Moreover, we identify a non-monotonicity issue affecting floating point multi-operand adders if the intermediate results are not normalized after each step.

RETRACTED ARTICLE: A novel cognitive Wallace compressor based multi operand adders in CNN architecture for FPGA

Convolutional neural networks is one of the most popular method in recent times to solve the computer vision and image processing applications. CNN has become more intensive as its computation increases day by day and it needs more dedicated hardware for an effective implementation. In recent times, graphics processing unit (GPU) and field programmable gate arrays (FPGA) are finding its high probability for the research in terms of low complexity execution and implementation of CNN. FPGA outperforms GPU in terms of its flexible architecture and high performance with less energy consumption. Hence FPGA finds more suitable for an effective implementation of CNN. How ever, optimization is required for an accelerator designs for CNN to accommodate more computations. One of the real dark side of the accelerator design is to perform the addition of intermediate results obtained during the convolution. Therefore multi operand adders are needed to employ for convolution operation but consumes the more area which in turn reduces the performance of the system. Hence the paper proposes the new cognitive Wallace compressor adder structures which is used for optimization in the adder layers of the convolutional neural networks (CNN). The proposed adders replaces the traditional binary tree adders for the CNN accelerator design. Also the paper provides the insight view of experimentation in ARTIX-7 EDGE FPGA and compared with the existing adders in which power consumption is reduced to 20–25% and area utilization has reduced to 30% respectively.

Area–delay and energy efficient multi‐operand binary tree adder

Here, the critical path of ripple carry adder (RCA)-based binary tree adder (BTA) is analysed to find the possibilities for delay minimisation. Based on the findings of the analysis, the new logic formulation and the corresponding design of RCA are proposed for the BTA. The comparison result shows that the proposed RCA design offers better efficiency in terms of area, delay and energy than the existing RCA. Using this RCA design, the BTA structure is proposed. The synthesis result reveals that the proposed 32-operand BTA provides the saving of 22.5% in area-delay product and 28.7% in energy-delay product over the recent Wallace tree adder which is the best among available multi-operand adders. The authors have also applied the proposed BTA in the recent multiplier designs to evaluate its performance. The synthesis result shows that the performance of multiplier designs improved significantly due to the use of proposed BTA. Therefore, the proposed BTA design can be a better choice to develop the area, delay and energy efficient digital systems for signal and image processing applications.

Efficient Model-Based Diagnosis of Sequential Circuits

In Model-Based Diagnosis (MBD), we concern ourselves with the health and safety of physical and software systems. Although we often use different knowledge representations and algorithms, some tools like satisfiability (SAT) solvers and temporal logics, are used in both domains. In this paper we introduce Finite Trace Next Logic (FTNL) models of sequential circuits and propose an enhanced algorithm for computing minimal-cardinality diagnoses. Existing state-of-the-art satisfiability algorithms for minimal diagnosis use Sorting Networks (SNs) for constraining the cardinality of the diagnostic candidates. In our approach we exploit Multi-Operand Adders (MOAs). Based on extensive tests with ISCAS-89 circuits, we found that MOAs enable Conjunctive Normal Form (CNF) encodings that are significantly more compact. These encodings lead to 19.7 to 67.6 times fewer variables and 18.4 to 62 times fewer clauses. For converting an FTNL model to CNF, we could achieve a speed-up ranging from 6.2 to 22.2. Using SNs fosters 3.4 to 5.5 times faster on-line satisfiability checking though. This makes MOAs preferable for applications where RAM and off-line time are more limited than on-line CPU time.

Implementation of multi-operand addition in FPGA using high-level synthesis

The paper presents the results of high-level synthesis (HLS) of multi-operand adders in FPGA using the Vivado Xilinx environment. The aim was to estimate the hardware amount and latency of adders described in C-code. The main task of the presented experiments was to compare the implementations of the carry-save adder (CSA) type multi-operand adders obtained as the effect of the HLS synthesis and those based on the basic component being 4-operand adder with fast carry-chain available in FPGA’s implemented in Verilog. However, the HLS synthesis simplifies the design and prototyping process but the received results indicate that the circuit obtained as the result of such synthesis requires twice more resources and is slower than its counterpart design using Verilog.

Decimal addition on FPGA based on a mixed BCD/excess-6 representation

Decimal arithmetic has recovered the attention in the field of computer arithmetic due to decimal precision requirements of application domains like financial, commercial and internet. In this paper, we propose a new decimal adder on FPGA based on a mixed BCD/excess-6 representation that improves the state-of-the-art decimal adders targeting high-end FPGAs. Using the proposed decimal adder, a multioperand adder and a mixed binary/decimal adder are also proposed. The results show that the new decimal adder is very efficient improving the area and delay of previous state of the art decimal adders, multioperand decimal addition and binary/decimal addition.

Limited Carry-Propagate Multiply-Accumulate Unit Design for Reconfigurable Systems

Counter and compressor arrays are frequently employed in multiplier design to efficiently reduce partial products in VLSI design. On the other hand, in reconfigurable systems, fast carry chains boost the performance of carry-propagate adders. So that, in reconfigurable systems, to save logic element area, counter and compressor trees are not employed as much since they require more area than carry-propagate scheme. In this work, carry-propagate multi-operand adders are employed in smaller blocks and the outputs are merged using double carry-save encoding to increase performance in reconfigurable systems. Hence, a more compact structure is achieved, compared to full redundant partial product reduction scheme providing comparable speed performance with counter array based carry-save structure. To show the effectiveness of the implementation, fused multiply-accumulate (MAC) units are designed for various bit-widths. The structure is implemented on AlteraTM Stratix III and Cyclone III FPGAs and the results show that, using least depth of pipeline, the throughput is better than regular carry-propagate and fully redundant carry-save reduction schemes.DOI: http://dx.doi.org/10.5755/j01.eie.23.2.17997

Design of RNS Reverse Converters with Constant Shifting to Residue Datapath Channels

This paper presents a new general approach to simplify residue-to-binary (reverse) converters for a Residue Number System (RNS) composed of an arbitrary set of moduli. It is suggested to formulate the basic equation of the reverse converter in a form consisting of two separate parts: one depending on input variables of the converter whereas the other is a single constant. Then, the constant, instead of being added inside the reverse converter, can be shifted out to the residue datapath channels, in most cases at no hardware cost or extra delay. Thus, the hardware cost of the converter is reduced, because its multi-operand adder has one operand less to handle. To illustrate various design issues of this new design approach and to prove its efficiency, a new design method of the residue-to-binary (reverse) converters for the 3-moduli set {2n−1,2n,2n+1} is considered. Two versions of the new converters for the 3-moduli set {2n−1,2n,2n+1} as well as several of their known counterparts were synthesized for all dynamic ranges from 8 to 38 bits (i.e., for 3 ≤ n ≤ 13). The results obtained suggest that, compared to the best of the state-of-the-art converters, at least one of two versions of our converters is superior with respect to area and power consumption, for all dynamic ranges considered, in some cases accompanied by slight delay reduction. The area is reduced from about 5 % to about 20 % and the largest savings are observed for the power consumption—from over 10 % up to 27 %.

Hierarchical Multipartite Function Evaluation

Function evaluation is an important arithmetic computation in many signal processing applications, such as special function units in modern graphics processing units (GPUs). Hardware implementations of function evaluation usually consists of lookup tables (LUT) and some simple arithmetic units of multipliers and/or adders. LUT usually takes a significant portion of total area cost, especially when function evaluators are allowed to compute several different arithmetic functions with shared arithmetic units where evaluation of each function needs separate LUT. In this paper, we focus on the category of table-addition (TA) function evaluators that are composed of two types of LUT, table of initial values ( TI ) and table of offset values ( TO ), followed by a multi-operand adder. It has been shown that multipartite table method (MP) has significant improvement over prior similar designs such as symmetric bipartite table methods (SBTM) and symmetric table addition methods (STAM) for applications with low-to-medium precision requirements. This paper presents an extension of MP, called hierarchical multipartite (HMP), which further reduces total table size by applying several levels of table decompositions. Furthermore, we perform the bit-width optimization by jointly considering the impacts of all error sources during the search of best table decompositions, leading to more efficient hardware design. Besides, a new lossless decomposition of TI is presented, resulting in additional saving of table size without incurring any extra errors. Experimental results show that the proposed design can efficiently reduce the total area cost in ASIC and FPGA implementations.

EXPERIMENTAL STUDIES ON MULTI-OPERAND ADDERS

Abstract In this paper, different multi-operand adders have been analyzed in terms of propagation delay, power consumption and resource utilization. The functionality of the adders have been verified using Verilog hardware description language and synthesized in Xilinx ISE. The device chosen for implementation is Virtex 6 (XC6VLX240T) with FF1156 package. Simulation results show that Wallace tree adder is the fastest adder and consumes least amount of power. The Wallace tree adder also consumes the least amount of hardware resources as per the synthesis results.

High Performance Multi-Operand Adder for Medical Images

AbstractThe Internet of Things (IoT) gives a new path for future Internet through which it had boosted the growth in number of devices ranging from home automation to medical devices. Security in IoT is a research topic, which involves security for low memory footprint devices. Hence light weighted cryptographic algorithms plays a major role in providing data integrity for IoT devices. The term light weightiness begins from gate level to system level. Multi-operand addition, which is widely used in block ciphers and hash functions. This work presents different approaches for realization of highly efficient multi-operand addition for medical IoT field devices. The use of conventional adders in the multipliers for summation of the intermediate results leads to area and delay overhead. Multi-operand addition and compressor trees can be used more efficiently for decimal operations, which will reduce the delay without much overhead in area. The proposed approach is experimented with different multipliers for i...

Hardware Efficient Architecture with Variable Block Size for Motion Estimation

Video coding standards such as MPEG-x and H.26x incorporate variable block size motion estimation (VBSME) which is highly time consuming and extremely complex from hardware implementation perspective due to huge computation. In this paper, we have discussed basic aspects of video coding and studied and compared existing architectures for VBSME. Various architectures with different pixel scanning pattern give a variety of performance results for motion vector (MV) generation, showing tradeoff between macroblock processed per second and resource requirement for computation. Aim of this paper is to design VBSME architecture which utilizes optimal resources to minimize chip area and offer adequate frame processing rate for real time implementation. Speed of computation can be improved by accessing 16 pixels of base macroblock of size 4 × 4 in single clock cycle using z scanning pattern. Widely adopted cost function for hardware implementation known as sum of absolute differences (SAD) is used for VBSME architecture with multiplexer based absolute difference calculator and partial summation term reduction (PSTR) based multioperand adders. Device utilization of proposed implementation is only 22k gates and it can process 179 HD (1920 × 1080) resolution frames in best case and 47 HD resolution frames in worst case per second. Due to such higher throughput design is well suitable for real time implementation.

Area efficient floating‐point FFT butterfly architectures based on multi‐operand adders

Hardware implementation of the fast Fourier transform (FFT) function consists of multiple consecutive arithmetic operations over complex numbers. Applying floating-point arithmetic to FFT coprocessors leads to a wider dynamic range and allows the coprocessor to collaborate with general purpose processors via the standard floating-point arithmetic. This offloads compute-intensive tasks from the primary processor and overcomes floating-point concerns such as scaling and overflow/underflow detection. The downside, however, is that floating-point units are slower than the fixed-point counterparts. One of the popular ways to improve the speed of floating-point FFT units is to merge the arithmetic operations inside the butterfly units of a FFT architecture. This leads to a butterfly architecture based on multi-operand adders. Butterfly units are designed, in two of the most recent works, using three-operand and four-operand adders. However, the work reported here by the present authors goes further and a butterfly architecture based on a five-operand adder is proposed. Simulation results demonstrate that the proposed butterfly architecture is 50% smaller than the fastest previous work with about 17% latency overhead. Compared with the smallest previous work, the proposed design is 47% smaller and 8% faster.

Table Size Reduction Methods for Faithfully Rounded Lookup-Table-Based Multiplierless Function Evaluation

Table-lookup-and-addition methods provide multiplierless function evaluation using multiple lookup tables and a multioperand adder. In spite of their high-speed operation, they are only practical in low-precision applications due to the fast increase in table size with precision width. In this brief, we present two methods for table size reduction by decomposing the original table of initial values into two or three tables with fewer entries and/or smaller bit width. The proposed table decompositions do not incur any extra rounding errors so that the original table can be completely recovered. Experimental results demonstrate significant saving of table sizes compared with the best of the prior designs of the multipartite methods.

Efficient architectures for modulo 2n − 2 arithmetic units

Moduli of the 2n and 2n ± 1 forms are usually employed in designs that adopt the residue number system. However, in several cases such as in finite impulse response filters and communication components, a modulo value equal to 2n − 2 can be used. So far, modulo 2n − 2 arithmetic units have been based either on look-up tables or on generic modulo arithmetic units. In this work, by taking advantage of the properties of modulo 2n − 2 arithmetic, we propose efficient modulo 2n − 2 multi-operand adder, multiplier as well as squarer architectures. The proposed circuits are based on the corresponding ones for modulo 2n−1 − 1 arithmetic and some simple logic. Experimental results validate that the proposed circuits achieve significant area and delay savings compared to those previously presented.

Multioperand Redundant Adders on FPGAs

Although redundant addition is widely used to design parallel multioperand adders for ASIC implementations, the use of redundant adders on Field Programmable Gate Arrays (FPGAs) has generally been avoided. The main reasons are the efficient implementation of carry propagate adders (CPAs) on these devices (due to their specialized carry-chain resources) as well as the area overhead of the redundant adders when they are implemented on FPGAs. This paper presents different approaches to the efficient implementation of generic carry-save compressor trees on FPGAs. They present a fast critical path, independent of bit width, with practically no area overhead compared to CPA trees. Along with the classic carry-save compressor tree, we present a novel linear array structure, which efficiently uses the fast carry-chain resources. This approach is defined in a parameterizable HDL code based on CPAs, which makes it compatible with any FPGA family or vendor. A detailed study is provided for a wide range of bit widths and large number of operands. Compared to binary and ternary CPA trees, speedups of up to 2.29 and 2.14 are achieved for 16-bit width and up to 3.81 and 3.11 for 64-bit width.