Abstract
Counter and compressor arrays are frequently employed in multiplier design to efficiently reduce partial products in VLSI design. On the other hand, in reconfigurable systems, fast carry chains boost the performance of carry-propagate adders. So that, in reconfigurable systems, to save logic element area, counter and compressor trees are not employed as much since they require more area than carry-propagate scheme. In this work, carry-propagate multi-operand adders are employed in smaller blocks and the outputs are merged using double carry-save encoding to increase performance in reconfigurable systems. Hence, a more compact structure is achieved, compared to full redundant partial product reduction scheme providing comparable speed performance with counter array based carry-save structure. To show the effectiveness of the implementation, fused multiply-accumulate (MAC) units are designed for various bit-widths. The structure is implemented on AlteraTM Stratix III and Cyclone III FPGAs and the results show that, using least depth of pipeline, the throughput is better than regular carry-propagate and fully redundant carry-save reduction schemes.DOI: http://dx.doi.org/10.5755/j01.eie.23.2.17997
Highlights
Multiplication and multiply-accumulate operations are most frequently used blocks in digital signal processing [1]– [4]
For high performance multiplier and MAC unit design, counter and compressor trees are mostly employed in VLSI design
As stated in [8], contemporary FPGA logic elements are configured in two modes as logic mode and arithmetic mode
Summary
Multiplication and multiply-accumulate operations are most frequently used blocks in digital signal processing [1]– [4]. For high performance multiplier and MAC unit design, counter and compressor trees are mostly employed in VLSI design It is not always the case in reconfigurable system design. In [8], various optimization methods are applied to implement various carry-save operators for partial product reduction and multi-operand addition. In [8] and [9] it is reported that (6, 3) counter arrays give best performance result for the reduction of partial products and multi-operand addition input operand reduction, whenever 6-input LUT structures are implemented. Multiple multi-operand carry-propagate adder blocks are implemented for the design on multiplyaccumulate (MAC) units. The outputs of the four multi-operand addition blocks are merged into a double carry-save structure. The multi-operand addition blocks can be pipelined in the structure to further improve the performance of the multiply accumulate unit. The proposed scheme provides best throughput performance with average area requirement
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