Motion Estimation Architecture Research Articles

On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture

This work explores the data reuse properties of full-search block-matching (FSBM) for motion estimation (ME) and associated architecture designs, as well as memory bandwidth requirements. Memory bandwidth in high-quality video is a major bottleneck to designing an implementable architecture because of large frame size and search range. First, the memory bandwidth in ME is analyzed and the problem is solved by exploring data reuse. Four levels are defined according to the degree of data reuse for previous frame access. With the highest level of data reuse, one-access for frame pixels is achieved. A scheduling strategy is also applied to data reuse of the ME architecture designs and a seven-type classification system is developed that can accommodate most published ME architectures. This classification can simplify the work of designers in designing more cost-effective ME architectures, while simultaneously minimizing memory bandwidth. Finally, a FSBM architecture suitable for high quality HDTV video with a minimum memory bandwidth feature is proposed. Our architecture is able to achieve 100% hardware efficiency while preserving minimum I/O pin count, low local memory size, and bandwidth.

Architecture for motion estimation using the one-dimensional hierarchical search block-matching algorithm

The realisation of a real-time video-coding system calls for a dedicated motion-estimation architecture. Whereas all the existing motion-estimation architectures offer either computational speed or hardware simplicity, in this paper, the authors propose an efficient pipelined parallel architecture for the one-dimensional hierarchical search (1DHS) block-matching algorithm that is efficient in terms of both speed and hardware cost. The architecture exploits the advantageous features of the 1DHS algorithm and makes use of an intelligent memory configuration to achieve high speed while keeping the hardware complexity low. The architecture also makes use of a data-reuse technique, thereby reducing the number of external memory accesses. The proposed architecture has been modelled in VHDL and simulated to establish its functional validity.

Low-Power 2D Motion Estimation Architecture with Complementary Embedded Memory Banks

This letter describes a motion estimation architecture with complementary access types of memory banks, one for column vector access and the other for row vector access. It handles 2D image very efficiently for full-search block matching algorithm and maximizes a useful data transfer rate by reducing the overhead clocks for extra data reading and alignment. The results show that power saving is improved by using complementary access types of memory banks and amounts to 27.3% when the full-search block matching algorithm is applied for the CCIR-601 format compared to an identical design without the proposed enhancements.

VLSI Architecture for Fast Motion Estimation Based on Bit-Plane Matching

In this paper, we propose a VLSI architecture for fast motion estimation based on bit-plane matching. The proposed architecture performs binary motion estimation using 1-bit plane image of the video sequence. The proposed motion estimator can be implemented using simple Boolean functions only, which can greatly reduce the hardware cost and the time overhead. Furthermore, the proposed architecture employs a pair of processing cores that calculate the motion vector continuously. By contolling the data ow in a systolic fashion using internal shift registers in the processing cores, we avoid using SRAM (local memory), so that we can remove the time overhead for accessing the local memory and/or adopt lower-cost fabrication technology. We modeled and tested the proposed motion estimator in VHDL, and then synthesized the whole system which has been integrated in a 0.6m triple-metal CMOS chip of size 8:15 10:84mm. Index Terms Video Compression, Fast Motion Estimation, VLSI Architecture

LOW-POWER 2D MOTION ESTIMATION ARCHITECTURE WITH COMPLEMENTARY EMBEDDED MEMORY BANKS

This letter describes a motion estimation architecture with complementary access types of memory banks, one for column vector access and the other for row vector access. It handles 2D image very efficiently for full-search block matching algorithm and maximizes a useful data transfer rate by reducing the overhead clocks for extra data reading and alignment. The results show that power saving is improved by using complementary access types of memory banks and amounts to 27.3% when the full-search block matching algorithm is applied for the CCIR-601 format compared to an identical design without the proposed enhancements.

An innovative, high quality and search window independent motion estimation algorithm and architecture for MPEG-2 encoding

This paper describes an innovative, pipelined, cache-based architecture for a motion estimation coprocessor. The coprocessor is based on a predictive/recursive algorithm whose computational complexity is low and not dependent on the search window. The synergies between the architecture and algorithm's features allow a high quality, low-area, low-bandwidth, search window implementation for standard resolution (PAL/NTSC), low resolution (CIF/QCIF) or high resolution (ATSC) sequences.

Robust velocity computation from a biologically motivated model of motion perception

Current computational models of motion processing in the primate motion pathway do not cope well with image sequences in which a moving pattern is superimposed upon a static texture. The use of non–linear operations and the need for contrast normalization in motion models mean that the separation of the influences of moving and static patterns on the motion computation is not trivial. Therefore, the response to the superposition of static and moving patterns provides an important means of testing various computational strategies. Here we describe a computational model of motion processing in the visual cortex, one of the advantages of which is that it is highly resistant to interference from static patterns.

Fast MPEG-4 Motion Estimation: Processor Based and Flexible VLSI Implementations

MPEG-4 is a new multimedia standard combining interactivity, object-based natural and synthetic digital video, audio and computer-graphics. For the implementation of the video part of the MPEG-4 standard a high degree of flexibility is required, where the motion estimation requires the highest part of the computational power. Therefore, in this paper fast algorithms for MPEG-4 motion estimation are evaluated in terms of visual quality and computational power requirements for processor based implementations. Due to the object-based nature of MPEG-4 also new VLSI architectures for MPEG-4 motion estimation are required. Therefore known motion estimation architectures are evaluated on their capability of being modified for MPEG-4 support. Based on this evaluation a new dedicated, but flexible MPEG-4 motion estimation architecture targeted for low-power handheld applications is presented, which resulted to be advantageous to processor based implementations by magnitudes of order.

Versatile architecture for block matching motion estimation

A novel architecture for the block matching technique is proposed, which can flexibly deal with various sizes of matching block and miscellaneous motion vector prediction modes of the current video coding standards, without extra area and control overhead. The processing element array of the proposed architecture features a separate difference and accumulation unit, considering the balanced delay time among operational data paths and efficient hardware resource utilisation. The VLSI realisation of the proposed architecture using 0.6μm CMOS technology shows significant improvement over a conventional systolic architecture in both area and speed.

A memory efficient array architecture for real-time motion estimation

A memory efficient array architecture for real-time motion estimation

A modular high-throughput architecture for logarithmic search block-matching motion estimation

A high-throughput modular architecture for a logarithmic search block-matching algorithm is presented. The design efforts are focused on exploiting the search area data dependencies using special data input ordering constraints. The input bandwidth problem has been solved by a random access on-chip memory, and a simple address generation procedure has been described. Furthermore, this architecture can handle a large search range with unequal horizontal and vertical spans using a technique called pipeline interleaving. Compared to the existing architectures for the three-step search BMA, this architecture delivers a high throughput rate with fewer input lines, and is linearly scalable.

A complete pipelined parallel CORDIC architecture for motion estimation

In this paper, a novel fully pipelined parallel CORDIC architecture is proposed for motion estimation. Unlike other block matching structures, it estimates motion in the discrete cosine transform (DCT) domain instead of the spatial domain. As a result, it achieves high system throughput and low hardware complexity as compared to the conventional motion estimation design in MPEG standards. That makes the proposed architecture very attractive in real-time high-speed video communication. Importantly, the DCT-based nature enables us not only to efficiently combine DCT and motion estimation units into a single component but also to replace all multiply-and-add operations in plane rotation by CORDICs to gain further savings in hardware complexity. Furthermore, this multiplier-free architecture is regular, modular, and has solely local connection suitable for VLSI implementation. The goal of the paper is to provide a solution for MPEG compatible video codec design on a dedicated single chip.

High Throughput, Scalable VLSI Architecture for Block Matching Motion Estimation

A VLSI architecture for the block matching motion estimation is described in this paper. The proposed architecture achieves 100% PE utilization and alleviates I/O bottleneck problem using small amount of distributed on-chip image memory. The number of processing elements is scalable according to the degree of parallel processing and throughput requirement. The overall computations are performed in pipelined manner and the data fill time for contiguous block is eliminated to increase throughput. The VLSI system implementation methodologies and the layouts are also described. Finally, the performances are evaluated and the advantages are outlined, compared to other architectures.

A low-power VLSI architecture for full-search block-matching motion estimation

This paper presents an architectural enhancement to reduce the power consumption of the full-search block-matching (FSBM) motion estimation. Our approach is based on eliminating unnecessary computation using conservative approximation. Augmenting the estimation technique to a conventional systolic-architecture-based VLSI motion estimation reduces the power consumption by a factor of 2, while still preserving the optimal solution and the throughput. A register-transfer level implementation as well as simulation results on benchmark video clips are presented.

Architectural Study of a Block-Recursive Motion Estimation Algorithm

The block-recursive algorithm for motion estimation is an option to classical methods like block-matching usually used in conventional coding schemes based on motion compensation. The block-recursive algorithm considered in this study as been developed at IRISA in the Temis group. It is composed of three steps: estimation, deterministic relaxation, and quadtree region splitting. These steps are iteratively executed until convergence.To be fully exploitable, a specialized VLSI architecture for motion estimation must satisfy the following features: real-time performance, modularity, easy external interfacing, flexibility and reduced internal complexity. In this paper, we analyse these different features with regards to the numerous parameters of the considered block-recursive algorithm. The influence of parameters on the quality of the coding algorithm is measured through numerous simulations. Architectural mechanisms required for an efficient implementation are also presented and discussed. This study falls within the framework for derivation of a specialized parallel architecture from the initial sequential algorithm specification.

Cost Effective VLSI Architectures for Full-SearchBlock-Matching Motion Estimation Algorithm

In this paper, we present efficient VLSI architectures for full-search block-matching motion estimation (BMME) algorithm. Given a search range, we partition it into sub-search arrays called tiles. By fully exploiting data dependency within a tile, efficient VLSI architectures can be obtained. Using the proposed VLSI architectures, all the block-matchings in a tile can be processed in parallel. All the tiles within a search range can be processed serially or concurrently depending on various requirements. With the consideration of processing speed, hardware cost, and I/O bandwidth, the optimal tile size for a specific video application is analyzed. By partitioning a search range into tiles with appropriate size, flexible VLSI designs with different throughput can be obtained. In this way, cost effective VLSI designs for a wide range of video applications, from H.261 to HDTV, can be achieved.

Low-complexity block-based motion estimation via one-bit transforms

We present an algorithm and a hardware architecture for block-based motion estimation that involves transforming video sequences from a multibit to a one-bit/pixel representation and then applying conventional motion estimation search strategies. This results in substantial reductions in arithmetic and hardware complexity and reduced power consumption, while maintaining good compression performance. Experimental results and a custom hardware design using a linear array of processing elements are also presented.

A VLSI architecture for hierarchical motion estimation

Motion estimation is the critical path in compression algorithms, and several dedicated hardware solutions have been proposed for its acceleration. In this paper we present an innovative VLSI architecture for motion estimation that combines a low implementation cost with real-time performance for videoconferencing and DTV standards. To minimize computational load and architecture requirements, we adopt a three-step hierarchical search algorithm, that provides a quality comparable with more expensive full-search techniques. The proposed solution focuses on architectural efficiency by employing a minimum set of functional units (three simple processing units, one minimum unit, and four programmable delay lines), still supporting real-time performance for videoconferencing standards. In addition we show how to combine parallel motion estimation units for backward-forward prediction (MPEG) and for higher throughput standards (DTV).< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Parallel programmable algorithm and architecture for real-time motion estimation of various video applications

This paper describes a parallel architecture for a new motion estimation algorithm that combines full search block matching with sparse search. Our solution caters to a wide variety of applications with various video data rates and various search ranges. Hence our architecture is programmable. Our solution also estimates the motion vector in real-time by using parallel processing. The multigrid algorithm works in maximum three sequential passes. Detailed data flow diagrams show the exact data use at every processor at every cycle time. This data flow is formalized with the derivation of exact analytic expressions. The 64-processor architecture consists of four clusters of 16 processors each, all working concurrently with each cluster working in a pipelined fashion. Novel hardware structures are designed to meet the data flow, requirements of the different passes. Enormous data reuse is performed to minimize the on-chip data storage. The novel VLSI architecture can easily be implemented on a single chip.

A novel modular systolic array architecture for full-search block matching motion estimation

A novel modular systolic array architecture for the full search block matching motion estimation algorithm (FBMA) is presented. The design efforts are focused on matching the array computation to system level input/output constraints. Compared to previously proposed FBMA architectures, this new architecture delivers highest throughput rate, achieves 100% processor utilization, requires much fewer input/output lines (pin count), and is linearly scalable. As such, this architecture offers a feasible solution for progressive-scan HDTV picture format. >