Abstract

The block-recursive algorithm for motion estimation is an option to classical methods like block-matching usually used in conventional coding schemes based on motion compensation. The block-recursive algorithm considered in this study as been developed at IRISA in the Temis group. It is composed of three steps: estimation, deterministic relaxation, and quadtree region splitting. These steps are iteratively executed until convergence.To be fully exploitable, a specialized VLSI architecture for motion estimation must satisfy the following features: real-time performance, modularity, easy external interfacing, flexibility and reduced internal complexity. In this paper, we analyse these different features with regards to the numerous parameters of the considered block-recursive algorithm. The influence of parameters on the quality of the coding algorithm is measured through numerous simulations. Architectural mechanisms required for an efficient implementation are also presented and discussed. This study falls within the framework for derivation of a specialized parallel architecture from the initial sequential algorithm specification.

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