Abstract
This paper describes a parallel architecture for a new motion estimation algorithm that combines full search block matching with sparse search. Our solution caters to a wide variety of applications with various video data rates and various search ranges. Hence our architecture is programmable. Our solution also estimates the motion vector in real-time by using parallel processing. The multigrid algorithm works in maximum three sequential passes. Detailed data flow diagrams show the exact data use at every processor at every cycle time. This data flow is formalized with the derivation of exact analytic expressions. The 64-processor architecture consists of four clusters of 16 processors each, all working concurrently with each cluster working in a pipelined fashion. Novel hardware structures are designed to meet the data flow, requirements of the different passes. Enormous data reuse is performed to minimize the on-chip data storage. The novel VLSI architecture can easily be implemented on a single chip.
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