MoS2 Transistors Research Articles

Versatile Triboiontronic Transistor via Proton Conductor.

Iontronics are effective in modulating electrical properties through the electric double layers (EDLs) assisted with ionic migration/arrangement, which are highly promising for unconventional electronics, ionic sensory devices, and flexible interactive interface. Proton conductors with the smallest and most abundant protons (H+) can realize a faster migration/polarization under electric field to form the EDL with higher capacitance. Here, a versatile triboiontronic MoS2 transistor via proton conductor by sophisticated combination of triboelectric modulation and protons migration has been demonstrated. This device utilizes triboelectric potential originated from mechanical displacement to modulate the electrical properties of transistors via protons migration/accumulation. It shows superior electrical properties, including high current on/off ratio over 106, low cutoff current (∼0.04 pA), and steep switching properties (89 μm/dec). Pioneering noise tests are conducted to the tribotronic devices to exclude the possible noise interference introduced by mechanical displacement. The versatile triboiontronic MoS2 transistor via proton conductor has been utilized for mechanical behavior derived logic devices and an artificial sensory neuron system. This work represents the reliable and effective triboelectric potential modulation on electronic transportation through protonic dielectrics, which is highly desired for theoretical study of tribotronic gating, active mechanosensation, self-powered electronic skin, artificial intelligence, etc.

All-inkjet-printed high-performance flexible MoS2 and MoS2-reduced graphene oxide field-effect transistors

Two-dimensional (2D) materials have been utilized to design flexible field-effect transistors (FETs) with promising performance. However, flexible FETs still face challenges with poor switching features and ultra-low drive current. In this paper, a facile and repeatable large-area integration process is presented for inkjet-printed FETs with 2D materials active channels and PI films as gate dielectrics. The MoS2 FETs reported here exhibit n-type channel feature with an outstanding average subthreshold swing of 75 mV/dec, an on-state/off-state current ratio of 104, and on-state current up to 10 μA at a power supply voltage of 3.0 V. Besides, MoS2–rGO FETs also exhibit n-type semiconductor features with good electrical properties by the inkjet-printing technology.

Molybdenum Contacts to MoS2 Field‐Effect Transistors: Schottky Barrier Extraction, Electrical Transport, and Low‐Frequency Noise

MoS2 has great interest for nanoscale electronic devices, including transistors and sensors. Defect‐free structure, clean interface with the gate dielectric, and metals with suitable metal–semiconductor junctions are key for reliable devices. Molybdenum is shown as an excellent electrode for MoS2 field‐effect transistors (FETs), but the correlation among device current, field‐effect mobility, and the low‐frequency noise (LFN) with number of atomic layers is not studied. Furthermore, the impact of Mo/MoS2 Schottky barrier on electronic injection and scattering in the device needs to be understood. Herein, by studying the FETs with channels of different numbers of atomic‐layer thicknesses, it is shown that a molybdenum metal contact to MoS2 provides reliable current injection with low Schottky barrier height, low contact resistance, low electron–phonon scattering, and negligible impurity scattering. The mobility and LFN are optimal at a channel thickness of ≈12 atomic layers, which is consistent with the “mobility maximum window” in MoS2 transistors with prior studies using other contact metals.

Characteristics of Cl-doped MoS2 field-effect transistors

MoS2 is among the two-dimensional (2D) transition metal dichalcogenides (TMD) and has been studied as a potential semiconductor material for various devices. To increase the performance of MoS2-based devices, contact engineering of metal to TMD materials has recently become an area of focus. The doping method is one way to reduce resistance, and molecular doping is a suitable doping method for MoS2 with a very thin layer structure. We demonstrate controllable molecular doping on MoS2 transistors using 1,2 dichloroethane (DCE) solution. Chloride molecules contained within the DCE solution act as an n-type dopant and increase the carrier density. The doping effects were confirmed by Raman spectroscopy, X-ray photoelectron spectroscopy, and current-voltage characteristics. We observed that the threshold voltages shifted toward the negative direction, implying electron doping of MoS2 after Cl-doping. Additionally, the field-effect mobility and the carrier densities were enhanced from 11.9 cm2·V−1·s−1 to 72.8 cm2·V−1·s−1 and from 3.62 × 1011 cm-2 to 1.37 × 1012 cm-2, respectively, by increasing the molar concentration of 1,2-dichloroethane solution to 12.6 M.

Stable Hysteresis-Free MoS2 Transistors With Low-k/High-k Bilayer Gate Dielectrics

Hysteresis-free and low-voltage operation are essential for low-power-consumption electronics. Herein, MoS2 transistors configured with bilayer-stacked polymethyl methacrylate (PMMA)/poly (vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) gate dielectric are demonstrated, which leverages the advantages of the hysteresis-free characteristic of PMMA and high- ${k}$ property of P(VDF-TrFE). The trap density and the threshold voltage of the devices can be reduced to $7.0\times 10^{11}$ cm $^{-2}\cdot eV^{-1}$ and −2.2 V, respectively. Moreover, the devices maintain stable performance under bias stress conditions. The devices present negligibly changed transfer and output characteristics over 101 cycling tests, indicating excellent stability. The bilayered dielectric engineering strategy provides a promising avenue to achieve hysteresis-free low-power operation in 2D materials based transistors with high stability.

Channel-protecting fabrication of top-gate MoS2 transistor arrays

The surface passivation on MoS2 and other transition metal dichalcogenides (TMDs) has been widely studied and utilized to prevent contamination and oxygen/water vapor penetration. Such approaches are mostly applied on the back-gate transistors after the formation of source/drain electrodes, while the compatibility in constructing top-gate devices has not yet been experimentally explored. Here, based on the large-area MoS2 thin film prepared with the atomic layer deposition technique, we developed an experimental routine to fabricate top-gate MoS2 thin-film transistor arrays with the TMD channel protected by high-k dielectric during the entire device fabrication process. The channel protection is enabled by the high-quality Al2O3 dielectric with proper pretreatment. The transistors in the array have shown enhanced electrical performance compared to the non-protected devices. Such a robust and well-controlled fabrication technique is a typical case of developing functional electronic devices by leveraging the strength of top-down lithography and the unique advantage of bottom-up growth, which can be further extended to the wide application in higher-level systems based on TMD materials.

Laser annealing towards high-performance monolayer MoS2 and WSe2 field effect transistors

The transition metal dichalcogenides (TMDCs) have been intensively investigated as promising nanoelectronic and optoelectronic materials. However, the pervasive adsorbates on the surfaces of monolayer TMDCs, including oxygen and water molecules from the ambient environment, tend to degrade the device performance, thus hindering specific applications. In this work, we report the effect of laser irradiation on the transport and photoresponse of monolayer MoS2 and WSe2 devices, and this laser annealing process is demonstrated as a straightforward approach to remove physically adsorbed contaminants. Compared to vacuum pumping and in situ thermal annealing treatments, the field-effect transistors after laser annealing show a more than one order of magnitude higher on-state current, and no apparent degradation of device performance at low temperatures. The mobility of the monolayer WSe2 devices can be enhanced by three to four times, and for single-layered MoS2 devices with the commonly used SiO2 as the back-gate, the mobility increases by 20 times, reaching . The efficient cleaning effect of laser annealing is also supported by the reduction of channel and contact resistance revealed by a transmission line experiment. Further, an enhanced photocurrent, by a factor of ten, has been obtained in the laser annealed device. These findings pave the way for high-performance monolayer TMDC-based electronic and optoelectronic devices with a clean surface and intrinsic properties.

Tuning the on/off current ratio in ionic-liquid gated multi-layer MoS2 field-effect transistors

Ionic-liquid gated multi-layer MoS2 field-effect transistors were fabricated and their electrical properties related to maximum depletion depth, bulk neutral and surface accumulation conduction were investigated in detail. A negative back-gate bias resulted in a depletion of the bulk neutral channel at the bottom interface, which significantly enhanced transistor performance in terms of the on-current to off-current (Ion/Ioff) ratio and the off-state current level. The experimental results were verified by numerical simulations and analytical equations. These findings are critical for the optimization of the Ion/Ioff ratio of multi-layer MoS2 transistors for energy efficient electronics and low power applications.

(Invited) Multi-Level Non-Volatile Memory in Au/Monolayer MoS2/Au Structures

The wide range of electronic and optical properties exhibited by two dimensional semiconductors, and their variation physical thickness, opens up new possibilities to create ultra-short length transistors [1], steep-slope switches [2, 3], light detecting/emitting devices [4, 5] and chemical/physical sensors. Recently, it was demonstrated that monolayer 2D semiconductors can also display resistive switching [6]. In this work we demonstrate that a single layer of large area CVD-grown moly disulphide (MoS2) sandwiched between two metal electrodes can be tuned to exhibit multi-level non-volatile resistive memory, with resistance values separated by 5 orders of magnitude. The switching process is unipolar and thermochemically driven (TCM memory) requiring significant Joule heating in the RESET process. Temperature dependent electrical measurements will be presented which demonstrate the charge transport mechanism varies between the initial state (IS), the high resistive state (HRS) and low resistive state (LRS). The temperature dependent behavior of the SET, RESET process is consistent with the creation and passivation of sulfur vacancies in the MoS2 monolayer. Conductive AFM measurements confirm that the multi-filamentary resistive memory effects are inherent to a single crystalline MoS2 triangle and not necessarily dependent of grain boundaries. This work demonstrates that potential for 2 terminal, multi-state, resistive memories for next generation digital memory and neuromorphic applications.[1] S. B. Desai et al., "MoS2 transistors with 1-nanometer gate lengths," Science, vol. 354, no. 6308, pp. 99-102, 2016.[2] S. Bhattacharjee, K. L. Ganapathi, S. Mohan, and N. Bhat, "A sub-thermionic MoS2 FET with tunable transport," Applied Physics Letters, vol. 111, no. 16, p. 163501, 2017.[3] D. Sarkar et al., "A subthermionic tunnel field-effect transistor with an atomically thin channel," Nature, vol. 526, no. 7571, p. 91, 2015.[4] K. Roy et al., "Graphene–MoS 2 hybrid structures for multifunctional photoresponsive memory devices," Nature nanotechnology, vol. 8, no. 11, p. 826, 2013.[5] X. Zhou et al., "2D Layered Material‐Based van der Waals Heterostructures for Optoelectronics," Advanced Functional Materials, vol. 28, no. 14, p. 1706587, 2018.[6] R. Ge et al., "Atomristor: Nonvolatile Resistance Switching in Atomic Sheets of Transition Metal Dichalcogenides," Nano letters, vol. 18, no. 1, pp. 434-441, 2017.

Multifunctional MoS2 Transistors with Electrolyte Gel Gating.

MoS2 , one of the most valued 2D materials beyond graphene, shows potential for future applications in postsilicon digital electronics and optoelectronics. However, achieving hole transport in MoS2 , which is dominated by electron transport, is always a challenge. Here, MoS2 transistors gated by electrolyte gel exhibit the characteristics of hole and electron transport, a high on/off ratio over 105 , and a low subthreshold swing below 50 mV per decade. Due to the electrolyte gel, the density of electrons and holes in the MoS2 channel reaches ≈9 × 1013 and 8.85 × 1013 cm-2 , respectively. The electrolyte gel-assisted MoS2 phototransistor exhibits adjustable positive and negative photoconductive effects. Additionally, the MoS2 p-n homojunction diode affected by electrolyte gel shows high performance and a rectification ratio over 107 . These results demonstrate that modifying the conductance of MoS2 through electrolyte gel has great potential in highly integrated electronics and optoelectronic photodetectors.

Local photodoping in monolayer MoS2

Inducing electrostatic doping in 2D materials by laser exposure (photodoping effect) is an exciting route to tune optoelectronic phenomena. However, there is a lack of investigation concerning in what respect the action of photodoping in optoelectronic devices is local. Here, we employ scanning photocurrent microscopy (SPCM) techniques to investigate how a permanent photodoping modulates the photocurrent generation in MoS2 transistors locally. We claim that the photodoping fills the electronic states in MoS2 conduction band, preventing the photon-absorption and the photocurrent generation by the MoS2 sheet. Moreover, by comparing the persistent photocurrent (PPC) generation of MoS2 on top of different substrates, we elucidate that the interface between the material used for the gate and the insulator (gate-insulator interface) is essential for the photodoping generation. Our work gives a step forward to the understanding of the photodoping effect in MoS2 transistors and the implementation of such an effect in integrated devices.

Thickness effect on low-power driving of MoS2 transistors in balanced double-gate fields

In field-effect transistors (FETs), when the thickness of the semiconducting transition metal dichalcogenides (TMDs) channel exceeds the maximum depletion depth, the entire region cannot be completely controlled by a single-gate electric field. The layer-to-layer carrier transitions between the van der Waals interacted TMD layers result in the extraordinary anisotropic carrier transport in the in-plane and out-of-plane directions. The performance of the TMD FETs can be largely enhanced by optimizing the thickness of the TMD channel as well as increasing the effective channel area through which the gate field is delivered. In this study, we investigated the carrier behavior and device performance in double-gate FETs fabricated using a 57 nm thick MoS2, which is thicker than the maximum depletion depth of about 50 nm, and a much thinner 4 nm thick MoS2. The results showed that in the thick MoS2, the gate voltages at both ends formed two independent channels which had no synergistic effect on the device performance owing to the inefficient delivery of the vertical electric field. On the other hand, in the thin MoS2 channel, the double-gate voltages effectively controlled one channel, resulting in twice the carrier mobility and operation in a low electric field region, i.e. below 0.2 MV cm−1.

Dual‐Gated MoS2 Transistors for Synaptic and Programmable Logic Functions

AbstractNeuromorphic computers, which can store information and compute at the same time, have been considered to be a potential candidate for greatly improving computing efficiency. The development of high‐performance artificial synapses, which are the basic unit of brain‐like chips, is very important for realizing efficient neuromorphic computing. Here, a dual‐gated MoS2 transistor is designed to realize synaptic functions and programmable logic operations. The channel conductance is modulated via top electrolyte gating to mimic important synaptic functions, such as excitatory postsynaptic current, paired‐pulse facilitation, and spike‐timing dependent plasticity. The synaptic transistor exhibits ultra‐low energy consumption with 12.7 fJ. Furthermore, the MoS2 transistor can dynamically reconfigure the logic operations of “AND,” “OR,” and “NOT” by combining top electrolyte gating with back gating. Classical Pavlov's dog experiment can be simulated by the dual gated device. These results indicate that the proposed synaptic transistor has potential applications in realizing neuromorphic and programmable logic devices.

Investigating the transient response of Schottky barrier back-gated MoS2 transistors

Molybdenum disulfide (MoS2) MOSFETs have been widely reported to exhibit hysteresis behavior, which is usually attributed to charge trapping effects due to defective/sub-stoichiometric compositions in the material, or defects near, or at, the oxide/channel interfaces. It is also suggested that defective MoS2 transistors show current limitations caused by the Schottky barrier junctions formed at the contacts. Here, we report on the static and dynamic device response of back-gated MoS2 transistors directly fabricated on a SiO2/Si substrate using chemical vapor deposition synthesis, without film transfer, and standard CMOS optical lithography. The devices exhibit an atypical hysteresis in the transfer characteristics, as well as a delayed response in the formation of the conducting channel in response to voltage pulses applied to the back gate. Analysis of the output characteristic is consistent with two back-to-back Schottky diodes, allowing the Fermi level pinning position at the Ni/MoS2 source and drain contacts and blocking the MoS2 hole channel. Capacitance-voltage characterization demonstrates that the grown MoS2 thin film is p-type, resulting in a nominally-off, inversion mode, n-channel device. Analysis of the transient response and hysteresis as a function of device temperature, illumination and ambient conditions indicates that the dynamic response of the device is determined by the net charge in the MoS2 film combined with the minority carrier generation lifetime in the underlying silicon substrate. The work demonstrates the strong dependence of the device response time on substrate, temperature, illumination, and net charge in the MoS2 layer opening the possibility of applications in photo-detectors and sensors.

Selective etching in graphene–MoS2 heterostructures for fabricating graphene-contacted MoS2 transistors

Semiconducting molybdenum disulfide (MoS2) has drawn a lot of attention for its exceptional electronic and optoelectronic properties. Despite the potential advantages, the large contact resistance at the metal–MoS2 interfaces has been one of the biggest obstacles for the realization of ideal MoS2 transistors. One solution to improve the metal–MoS2 interfaces is to use the graphene electrodes. Here, we provide a selective etching method for fabricating graphene-contacted MoS2 transistors. It has been proved that the graphene could be totally etched with Ar+ plasma treatment, and the multilayer MoS2 flake can also be reduced layer by layer with Ar+ plasma treatment. By etching graphene selectively in graphene–MoS2 heterostructures, one can obtain graphene-contacted MoS2 transistors successfully. The transistor reported in this paper shows an on–off ratio about 106 and a carrier mobility about 42 cm2 V−1 s−1. This selective etching method would be beneficial for some other graphene-contacted electronic devices.

Improved Interfacial and Electrical Properties of MoS2Transistor With High/Low-Temperature Grown Hf0.5Al0.5O as Top-Gate Dielectric

Uniform Hf0.5Al0.5O top-gate (TG) dielectric can be grown directly on the MoS2 surface using a high/low-temperature deposition method, and excellent performances for few-layer (FL) MoS2 transistors with Hf0.5Al0.5O as TG dielectric can be achieved: high mobility of 90 cm2/Vs, small sub-threshold swing of 77 mV/dec and low interface-state density of $1.08\times {10}^{{12}}$ eV−1cm−2. The involved mechanisms lie in the facts that (1) the TG dielectric can prevent the MoS2 surface from absorbing the oxygen and moisture in the air; (2) growing the Hf0.5Al0.5O dielectric at low temperature can well provide nucleation sites for its subsequent high-temperature growth; and (3) doping Al into HfO2 can reduce the trap charges in the resulting HfAlO dielectric to weaken the Coulomb scattering and also produce densified and uniform dielectric film. Therefore, the Hf0.5Al0.5O TG-dielectric structure and its growth method described in this work have a high potential to fabricate high-performance FL MoS2 field-effect transistors for practical electron device applications.

Long-term stability of multilayer MoS2 transistors with mica gate dielectric

To avoid surface damage of a MoS2 channel, a mica flake with high permittivity and atomically flat surface was dry transferred onto a multilayer MoS2 flake to prepare top-gated transistors. For the first time, the interface properties of mica/MoS2 and the long-term stability of devices were investigated when the transistors were exposed to ambient air. Results show that the electrical performance of the transistors is degraded significantly when the devices are exposed to ambient moisture for a long time, due to the strong hydrophilism of mica. The transfer curves of the transistors cannot be recovered to their initial states even after annealing. The adsorbed moisture can become trapped at the interface between the MoS2 channel and mica dielectric or on the MoS2 surface, resulting in enhanced carrier scattering and degraded device performance. However, the top-gated MoS2 transistor with Al2O3 encapsulation exhibits enhanced stability even after annealing or exposure to atmosphere for 200 days. The excellent stability should be attributed to the effective insulation of moisture from the ambient air by Al2O3 encapsulation. Therefore, a dense and hydrophobic encapsulation layer is indispensable for stable and high-performance top-gated MoS2 transistors with mica gate dielectric.

Multilayer Si shadow mask processing of wafer-scale MoS2 devices

Two-dimensional layered materials (2DLMs) have attracted great research interest due to their exotic physical properties and potential applications in nanoelectronics and optoelectronics. Device fabrication with 2DLMs is challenging because their ultrathin characteristic makes them extremely sensitive to the external environment, especially to chemical contamination introduced by optical lithography. The shadow mask technique is a clean alternative in lithography-free electrode patterning for emerging nanomaterials. However, shadow mask assisted fabrication over large areas and multilevel alignment of patterns remain challenging for practical applications. In this paper, we report an over wafer scale shadow mask fabrication technique for 2DLMs. Based on successful fabrication of customized silicon shadow masks with micrometer feature sizes, their advantages for fabricating higher mobility and lower interface trapped exfoliated MoS2 transistors are demonstrated. Meanwhile, applications in large-scale metal deposition and sample etching are also explored. The max alignment error of multilayer patterns fall in 0.5–3.0 µm in x- and 2.0–9.0 µm in y -directions. Then this technique is employed to realize a fabrication of MoS2 top-gated field effect transistor arrays with two universal strategies: ‘etching-last’ and ‘channel-first’ on 1 × 1 cm2 Al2O3 substrate. Furthermore, logic inverter circuits with a high gain of 10 are successfully fabricated. The results provide an alternative as a universal, low-cost, time-saving method for fabricating large-scale 2DLM electronics and flexible electronics.

Controllable Doping of Transition‐Metal Dichalcogenides by Organic Solvents

AbstractSeeking controllable and efficient surface dopant molecules for transition‐metal dichalcogenides (TMDCs) is highly valuable for fully understanding TMDCs properties and their applications to relevant devices. The general doping effect of solvents on TMDCs are explored. By selecting suitable solvents with optimized relevant factors, controllable n‐doping of molybdenum disulfide (MoS2) is obtained on the same device with the sheet density of electrons increased from 2.3 × 1011 to 6.4 × 1012, 9.7 × 1012, and 1.6 × 1013 by use of dimethylsulfoxide, N,N‐dimethylformamide, and N‐methyl‐pyrrolidone (NMP), respectively. The doping principle is explained by charge‐donating characteristics of molecule and dipole interaction. After doping by NMP, the contact resistance is reduced by four times, and the on/off current ratio of fabricated top‐gated MoS2 transistors is increased by 3 orders of magnitude. This work can guide the selection of suitable solvents for effective doping of two‐dimensional materials and advance the development of precise controllable electronic and optoelectronic devices.

Optimizing Al-doped ZrO2 as the gate dielectric for MoS2 field-effect transistors

In this work, we investigate the effects on the electrical properties of few-layered MoS2 field-effect transistors (FETs) following Al incorporation into ZrO2 as the gate dielectrics of the devices. A large improvement in device performance is achieved with the Al-doped ZrO2 gate dielectric when Zr:Al = 1:1. The relevant MoS2 transistor exhibits the best electrical characteristics: high carrier mobility of 40.6 cm2 V−1 s−1 (41% higher than that of the control sample, and an intrinsic mobility of 68.0 cm2 V−1 s−1), a small subthreshold swing of 143 mV dec−1, high on/off current ratio of 6 × 106 and small threshold voltage of 0.71 V. These are attributed to the facts that (i) Al incorporation into ZrO2 can decrease its oxygen vacancies; densify the dielectric film; and smooth the gate dielectric surface, thus reducing the traps at/near the Zr0.5Al0.5Oy/MoS2 interface and the gate leakage current; (ii) adjusting the dielectric constant of the gate dielectric to an appropriate value, which achieves a reasonable trade-off between the gate screening effect on the Coulomb-impurity scattering and the surface optical phonon scattering. These results demonstrate that optimized Zr0.5Al0.5Oy is a potential gate dielectric material for MoS2 FET applications.