Stable Hysteresis-Free MoS2 Transistors With Low-k/High-k Bilayer Gate Dielectrics

Abstract

Hysteresis-free and low-voltage operation are essential for low-power-consumption electronics. Herein, MoS2 transistors configured with bilayer-stacked polymethyl methacrylate (PMMA)/poly (vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) gate dielectric are demonstrated, which leverages the advantages of the hysteresis-free characteristic of PMMA and high- ${k}$ property of P(VDF-TrFE). The trap density and the threshold voltage of the devices can be reduced to $7.0\times 10^{11}$ cm $^{-2}\cdot eV^{-1}$ and −2.2 V, respectively. Moreover, the devices maintain stable performance under bias stress conditions. The devices present negligibly changed transfer and output characteristics over 101 cycling tests, indicating excellent stability. The bilayered dielectric engineering strategy provides a promising avenue to achieve hysteresis-free low-power operation in 2D materials based transistors with high stability.