Annealing temperature effects on the electrical characteristics of p-channel polysilicon thin film transistors

Abstract

In this work, we studied the effects of different thermal annealing on the electrical characteristics of non-self-aligned low-temperature p-channel polycrystalline silicon (polysilicon) thin film transistors. Different thermal treatments were performed after Al-gate formation at different temperature (200°C, 250°C, 350°C and 450°C) and annealing times. We found that optimal conditions were obtained at 350°C, with transfer characteristics showing a subthreshold slope of 0.5V/dec, field effect mobility >100cm2/Vs and threshold voltage around −3.5V. Hot carrier induced degradation was also analyzed performing bias-stress measurements on devices annealed at 350°C and at different bias stress conditions. The experimental data show that a maximum transconductance degradation is obtained for Vg(stress)−Vt=−4V while bias-stress at Vg=Vt and ∣Vg(stress)∣≫∣Vds(stress)∣ did not produce appreciable changes in both transfer and output characteristics.