Effective channel length and parasitic resistance determination in non self-aligned low temperature polycrystalline silicon thin film transistors

Abstract

The presence of high electric fields at the drain junction in polycrystalline silicon (polysilicon) thin film transistors (TFTs), enhances several undesired effects, such as hot-carrier related instabilities and kink effect. In order to reduce the drain electric field, non-self-aligned (NSA) device architecture can be adopted. In this case, dopant activation and active layer crystallization are achieved at the same time by excimer laser annealing, resulting in a substantial lateral dopant diffusion. The gradual doping profile provides not only a reduction of the drain electric field, but also a channel length shortening. Therefore, an effective channel length ( L eff) has to be determined in such devices, in order to successfully design circuit applications. In this work, L eff and parasitic resistance ( R p) modulation effects have been investigated in both n- and p-channel NSA polysilicon TFTs. Three different parameter extraction methods, originally proposed for the crystalline MOSFETs technology, have been used and compared in order to extract L eff and R p, including: the “channel resistance” method; the “paired V g” method; the “shift and ratio” method. These methods indicate a channel length reduction up to 1 μm and a non negligible parasitic resistance effect. The reliability of the results of the three methods are discussed in terms of applicability of the underlying assumptions in the case of polysilicon TFTs and numerical simulations are used to support the analysis.