MOS Transistor Structure Research Articles

The Mathematical Model of Radio-measuring Frequency Transducer of Optical Radiation Based on MOS Transistor Structures with Negative Differential Resistance

The Mathematical Model of Radio-measuring Frequency Transducer of Optical Radiation Based on MOS Transistor Structures with Negative Differential Resistance

Charge Properties of the MOS Transistor Structure with the Channel Made from a Two-Dimensional Crystal

Two-dimensional (2D) semiconductor crystals can be applied to further increase the efficiency and speed of field-effect transistors. Such transistors are free from some of the adverse effects present in the traditional MOS transistors when their size is reduced. In this study, the model of the transistor MOS structure with the channel made of a 2D-crystal is proposed and its charge properties are investigated. The numerical simulation of such characteristics is carried out within the range of variations of the electrophysical properties of 2D-crystals representative of MoSe2, WS2, WSe2, ZrSe2, HfSe2, and PtTe2. The self-consistent correlation between electrophysical parameters of the structure via the chemical potential is found, and the effect of the potential of the field electrode and the gate insulator’s capacitance on them is demonstrated. The calculations of the steepness of the transfer characteristic and the voltage gain of such a transistor structure demonstrate that, for the channel made from transition metal dichalcogenides (TMD) with the forbidden gap band falling in the range 0.25–2.1 eV, the magnitudes of these parameters can attain 0.1 mA/V and 1000, respectively.

Зарядовые свойства транзисторной МОП-структуры с каналом из двумерного кристалла

Зарядовые свойства транзисторной МОП-структуры с каналом из двумерного кристалла

Hysteresis in Single-Layer MoS2 Field Effect Transistors

Field effect transistors using ultrathin molybdenum disulfide (MoS(2)) have recently been experimentally demonstrated, which show promising potential for advanced electronics. However, large variations like hysteresis, presumably due to extrinsic/environmental effects, are often observed in MoS(2) devices measured under ambient environment. Here, we report the origin of their hysteretic and transient behaviors and suggest that hysteresis of MoS(2) field effect transistors is largely due to absorption of moisture on the surface and intensified by high photosensitivity of MoS(2). Uniform encapsulation of MoS(2) transistor structures with silicon nitride grown by plasma-enhanced chemical vapor deposition is effective in minimizing the hysteresis, while the device mobility is improved by over 1 order of magnitude.

High-voltage (100 V) Chipfilm<sup>TM</sup> single-crystal silicon LDMOS transistor for integrated driver circuits in flexible displays

Abstract. System-in-Foil (SiF) is an emerging field of large-area polymer electronics that employs new materials such as conductive polymers and electrophoretic micro-capsules (E-Ink) along with ultra-thin and thus flexible chips. In flexible displays, the integration of gate and source drivers onto the flexible part increases the yield and enhances the reliability of the system. In this work we propose a high-voltage ChipfilmTM lateral diffused MOS transistor (LDMOS) structure on ultra-thin single-crystalline silicon chips. The fabrication process is compatible with CMOS standard processing. This LDMOS structure proves to be well suited for providing adequately large switching voltages in spite of the thin (<10 μm) substrate. A breakdown voltage of more than 100 volts with drain-to-source saturation current Ids(sat)≈85 μA/μm for N-LDMOS and Ids(sat)≈20 μA/μm for P-LDMOS is predicted through process and device simulations.

A Double-Spacer I-MOS Transistor With Shallow Source Junction and Lightly Doped Drain for Reduced Operating Voltage and Enhanced Device Performance

In this letter, a double-spacer (DS) design is utilized for the formation of shallow source and lightly doped drain to further optimize the impact-ionization MOS (I-MOS) transistor structure. The breakdown voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BD</sub> needed for avalanche breakdown is lowered due to the shallow source extension. With the formation of the lightly doped drain extension, the impact of drain bias on breakdown voltage, and hence, the threshold voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> is also reduced. The DS I-MOS is fabricated and characterized. Detailed analysis and physical explanation of the impact of drain/gate bias on the device characteristics are provided. Compared to the conventional I-MOS transistor, the shallow source extension reduces the breakdown voltage [drain-induced breakdown voltage lowering (DIBVL)] by 0.3-0.6 V, and the lightly doped drain extension reduces the DIBVL up to 0.17 V/V. In addition, excellent subthreshold swing and good device performance are achieved.

Simulation and design of a germanium L-shaped impact-ionization MOS transistor

This paper reports a novel L-shaped impact-ionization MOS (LI-MOS) transistor structure that achieves a subthreshold swing of well below 60 mV/decade at room temperature and operates at a low supply voltage. The device features an L-shaped or an elevated impact-ionization region (I-region), which displaces the hot carrier activity away from the gate dielectric region to improve hot carrier reliability and VT stability problems. Germanium, which has a lower bandgap and impact-ionization threshold energy lower than silicon, is chosen as the material of choice for the LI-MOS transistor structure. Device physics and design principles for the LI-MOS transistor are detailed through extensive two-dimensional device simulations. The LI-MOS transistor exhibits excellent scalability, making it suitable for augmenting the performance of standard CMOS transistors in future technology generations.

Temperature dependences of surface recombination DC current–voltage characteristics in MOS structures

Temperature dependences of recombination current at interface traps in MOS transistor structure are investigated using the Shockley–Read–Hall Recombination DC current–voltage (R-DCIV) characteristics. Results include the effects of energy distribution of the interface traps (discrete, constant and U-shaped energy distributions) on the temperature dependence of the base terminal current-vs-gate-voltage lineshape (IB–VGB), the peak current and voltage (IB-peak, VGB-peak) and their thermal activation energy EA, and the reciprocal slope n of the IB-peak vs base/drain (or base/source) p/n junction forward voltage VBD. Surface impurity concentration and oxide thickness are varied. Temperature dependence of EA, VGB-peak and n is small while IB-peak and R-DCIV linewidth, large. This small temperature dependence simplifies the experimental implementation and data analysis of R-DCIV methodology applied at room temperatures without using expensive temperature controlled wafer-probe station.

A technique to improve the drive current of high-voltage I/O transistors in digital CMOS technologies

By combining a 0.12-μm-long 1.2-V thin-oxide transistor with a 0.22-μm-long 3.3-V thick-oxide transistor in a 0.13-μm CMOS process, a composite MOS transistor structure with a drawn gate length of 0.34 μm is realized. Measurements show that at V/sub GS/=1.2 V and V/sub DS/=3.3 V, the composite transistor has more than two times the drain current of the minimum channel length (0.34 μm) 3.3-V thick-oxide transistor, while having the same breakdown voltage (V/sub BK/) as the thick-oxide transistor. Exploiting these, it should be possible to implement 3.3-V I/O transistors with better combination of drive current, threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) and breakdown voltage in conventional CMOS technologies without adding any process modifications.

Improved neuron MOS-transistor structures for integrated neural network circuits

The neuron MOS transistor is a recently discovered device which is capable of executing a weighted sum calculation of multiple input signals and threshold operation based on the result of summation, thereby simulating the function of biological neurons. A comprehensive set of neuron test transistors has been designed, where a number of input gates are coupled capacitively to a floating gate, which controls the channel current. Integrated circuits for neural network applications have also been designed, based on the neuron MOS transistors. These circuits include neuron CMOS inverters and A/D and D/A converters. To increase the accuracy of the neuron MOSFET structures, calibration techniques are proposed and tested. All the test structures and circuits are implemented by using a standard 0.8 µm double-polysilicon CMOS technology. Attention was paid to saving of the layout area and reducing power consumption.

Improved analytical modeling of polysilicon depletion in MOSFETs for circuit simulation

Polysilicon gate depletion is an important effect that degrades the circuit performance of deep submicron standard CMOS technologies. A new approach to analytically modeling the polysilicon depletion effect on drain current and transconductances as well as node charges and transcapacitances is presented. The model is based on a clear physical analysis of the charges in the MOS transistor structure. Using the modeling framework and the fundamental variables of the EKV MOS transistor model formalism and that of the related charges models, a continuous model is achieved that is valid in all operating regions from weak inversion to strong inversion and from non-saturation to saturation. The asymptotic behavior of the transcapacitances is improved with respect to former model formulations. Only the doping concentration in the polygate is used in addition to the other physical device model parameters. The model shows excellent results in comparison with a surface potential based numerical model and 2D numerical device simulation. The model is efficient for circuit simulation and is further practical for analog circuit design.

The vertical heterojunction MOSFET

In this paper a new vertical MOS transistor structure including its fabrication and electrical results will be presented. It overcomes the technological and physical limitations encountered when scaling the classical planar transistor into the deep submicron regime. It solves the technological issue by defining the channel length through epitaxial growth instead of lithography. The physical phenomenon of drain induced barrier lowering (DIBL) is largely decreased through the use of a heterojunction between source and drain.

Reduction of complex MOS structures used in switch-level simulators

The ratio of a transistor's width to its length is the only geometric parameter available to design engineers that affects the performance of a MOS transistor. This ratio, known also as the shape factor, defines the transistor strength. Most switch-level simulators are built with knowledge of the transistor strength. In this paper, a theory that will provide a method for calculating the equivalent transistor strength (shape factor) of complex MOS transistor structures is developed. In the case of non-series-parallel MOS structures, this method includes a Y-to- Δ transformation which usually leads to a significant reduction of circuit complexity. The results obtained are applicable to both NMOS and CMOS structures. The method introduced is illustrated by examples. Computer simulation is also used to show the validity and effectiveness of the results obtained.

Power MOS devices: Structure evolutions and modelling approaches

In this survey paper, the historical evolution of power MOS transistor structures is presented and mostly used actual devices are described. General considerations on current and voltage capabilities are discussed and configuration of popular structures is given. It then presents a synthesis of different modelling approaches proposed in recent years. These include analytical solutions for basic electrical parameters, e.g. threshold voltage, on resistance, saturation and quasi-saturation effects, temperature impact and voltage handling capability. The numerical solutions of basic semiconductor devices are then briefly described along with some typical problems which can be solved this way. The compact circuit modelling method is finally explained with emphasis on dynamic behaviour modelling. Physical numerical models are detailed together with those intended for circuit simulation. A fairly exhaustive bibliography is given for completeness.

An offset-trimmable array of magnetic-field-sensitive MOS transistors (MAGFETs)

Magnetic-field sensors can be implemented by the use of a magnetic-field-sensitive MOSFET structure, commonly referred to as a MAGFET. The MAGFET is a split-drain MOSFET where the difference between the drain currents is dependent on the magnetic field applied to the MAGFET. Unfortunately, the sensitivity of the MAGFET is rather small and the inherent offset between the drain currents (at zero magnetic field) may well be of the same magnitude as the field-dependent current difference, even for fields of about 0.1 T. Hence, it is often necessary to introduce some sort of offset compensation. In this paper we present a new combination of an offset compensating circuit and a MAGFET cascade circuit with increased sensitivity. The offset compensation utilizes a digitally trimmable current mirror implemented by a multiple-gate MOS transistor structure. A prototype circuit has been fabricated in a 2.4 μm n-well CMOS technology. The measured results show that the offset is reduced by more than one order of magnitude.

Design method for a digitally trimmable MOS transistor structure

A digitally trimmable MOS transistor is a MOS transistor consisting of a drain a source and a main gate as well as several subgates. The transconductance of the transistor is digitally tunable by means of connecting subgates either to the main gate or to the source terminal. In the paper a systematic design method for a digitally trimmable MOS transistor structure is proposed. Using the proposed method, we have designed a digitally trimmable MOS transistor structure, and fabricated prototype devices in a 2.4μm n-well CMOS technology. Through measurement on these devices the design method has been experimentally confirmed. The trimmable MOS transistor structure has been applied to a high precision current mirror to reduce mismatch in the current mirror. With the trimmable transistor structure, the mismatch can be reduced by more than one order of magnitude.

Ion implantation in future MOS technology

Ion implantation in future MOS technology is examined by considering the anticipated changes in the MOS transistor structure over the next decade. The widely used LDD MOSFET will likely be phased out as the technology is scaled below 0.35 μm feature sizes. New structures and/or substantially reduced device operating voltages will be required, and possible approaches are described. The implications for ion implantation technology as well as additional observations of needs and opportunities are discussed. There is a critical need for improved understanding and models of ion implantation, in particular damage and its effect on impurity diffusion, the influence of all of the implant parameters on the resulting profile, implants through multiple layers of materials, and two- and three-dimensional effects.

Feasibility of very‐short‐channel mos transistors with double‐gate structure

AbstractConventionally, extremely thin gate oxide and high channel‐doping concentration are used to reduce the short channel effect of an MOS transistor below the submicron region. However, with these methods, there are problems such as the degradation in design freedom with respect to the breakdown voltage, the considerable decrease in the carrier mobility and the remarkable variation in characteristics of devices due to the statistical fluctuation of the impurity doping profile; and they need to be solved. Through the numerical analysis of the threshold voltage performance and the experimental fabrication of various devices with effective channel length range from 0.26 μm to 1.26 μm, it has been made clear in this paper that a double‐gate MOS transistor (XMOS) structure with another insulated gate at the lower part of the channel can reduce the short channel effect without the above‐mentioned problems. The results also show that the gate swing has reached about 60 mV/decade that is close to the theoretical limit; the short channel effect can even be reduced with a much shorter channel length if a thinner active channel layer is used and that reduction is independent of the channel doping concentration; and the limit to a possible shorter channel length may be less than 0.1 μm. It is concluded that the problems with the conventional MOS transistor can be solved by using XMOS structure.

Digitally tunable MOS-current mirrors for high precision applications

A high accuracy digitally tunable MOS transistor structure is proposed, and the working principle is verified experimentally. Experimental results on devices fabricated using a standard 3 μm p-well CMOS process show that the gain of the current mirrors using the proposed structure can be trimmed with an accuracy better than within 0.1%.

Performance of silicon trigger counters in the Megarad range

The response of p-i-n diodes and of novel pixel counters, capable of signal storage, to high radiation doses was studied systematically by means of 10-MeV proton beams scattered from gold foils. The leakage current shows a more than proportional increase with increasing dose and an exponential dependence on temperature. The cooled (-50 degrees C) p-i-n diodes remain operational at the highest dose of 17.6 Mrad. As specific radiation effects of the DEPMOS counter, incorporating a MOS transistor structure on a fully depleted bulk of 280- mu m thickness, shifts of the transmission characteristics and a decrease of the acceptance period of the internal gate which allows for nondestructive readout have been observed. Annealing at room temperature was studied for both detector types. >