The vertical heterojunction MOSFET

Abstract

In this paper a new vertical MOS transistor structure including its fabrication and electrical results will be presented. It overcomes the technological and physical limitations encountered when scaling the classical planar transistor into the deep submicron regime. It solves the technological issue by defining the channel length through epitaxial growth instead of lithography. The physical phenomenon of drain induced barrier lowering (DIBL) is largely decreased through the use of a heterojunction between source and drain.