MOS Capacitor Structures Research Articles

Electronic properties of ZrO2 films fabricated via atomic layer deposition on 4H-SiC and Si substrates

Being an important semiconductor material for high power applications, silicon carbide (SiC) faces the problems while used as a gate oxygen layer in traditional Si MOS devices. In view of this, an innovative approach was adopted in the present work to replace the conventional SiO2 with a high-k material (ZrO2) as the gate oxygen layer to investigate its effect on the electrical characteristics of the devices. In particular ZrO2 films were deposited on Si and SiC substrates by atomic layer deposition (ALD), and Al was used as the electrode. The atomic force microscopy (AFM) microregion scan revealed a highly flat surface with Rq < 1 nm after the ALD growth of ZrO2 layer. The sample surface analysis via x-ray photoelectron spectroscopy (XPS) suggested the presence of a small amount of ZrOx components. According to the electron energy loss spectrum (EELS), the band gap width (Eg) of this ALD ZrO2 dielectric was 5.45 eV, which met the requirements for high-quality 4H-SiC-related MOS devices. The electrical properties of the samples were then studied, and the maximum breakdown voltage of the Al/ZrO2/SiC/Al MOS structure was obtained to be 23 V, i.e., nearly twice that of the Si substrate. As for the oxide layer, the interface defect density (Dit) near the conduction band of the Al/ZrO2/SiC/Al MOS structure was only 1012 eV−1 cm−2 orders of magnitude. The Neff value (the movable charge) of the structure was also controlled at 1012 cm−2. Therefore, the overall performance of the ZrO2/SiC structure in terms of electrical properties exceeded that of the ZrO2/Si structure and previously reported counterparts. In this respect, the ZrO2/SiC MOS capacitor structure has great research potential.

Capacitor-Based Synaptic Devices for Hardware Spiking Neural Networks

In this work, we present a hardware neural network with capacitor-based synaptic devices. A capacitor-based synaptic device was developed using a MOS capacitor structure with a charge trapping layer. Due to the flat band voltage shift by charge trapping and its non-linear <inline-formula> <tex-math notation="LaTeX">${C} - {V}$ </tex-math></inline-formula> characteristics, multilevel weight values could be implemented by the charge occurring when charging and discharging the capacitor. The vector-matrix multiplication (VMM) function was also experimentally verified using a fabricated synapse array based on NAND flash structure.

Fully-Integrated Heterogeneous DML Transmitters for High-Performance Computing

Optical connectivity, which has been widely deployed in today's datacenters and high-performance computing (HPC) systems, is a disruptive technological revolution to the IT industry in the new Millennium. In our journey to debut an Exascale supercomputer, a completely new computing concept, called memory-driven computing, was innovated recently. This new computing architecture brings challenges and opportunities for novel optical interconnect solutions. Here, we first discuss our strategy to develop appropriate optical link solutions for different data traffic scenarios in memory-driven HPCs. Then, we present detailed review on recent work to demonstrate fully photonics-electronics-integrated single- and multi-wavelength directly modulated laser (DML) transmitters on silicon for the first time. Compact heterogeneous microring lasers and laser arrays were fabricated as photonic engines to work with a customized complementary metal-oxide semiconductor (CMOS) driver circuit. Microring lasers based on conventional quantum well and new quantum dot lasing medium were compared in the experiment. Thermal shunt and MOS capacitor structures were integrated into the lasers for effective thermal management and ultra low-energy tuning. It enables a controllable dense wavelength division multiplexing (DWDM) link architecture in an HPC environment. An equivalent microring laser circuit model was constructed to allow photonics-electronics co-simulation. Equalization functionality in the CMOS driver circuit proved to be critical to achieve up to 14 Gb/s direct modulation with 6 dB extinction ratio. Finally, the on-going and future work is discussed towards more robust, higher speed, and more energy efficient DML transmitters.

High Aspect Ratio β-Ga2O3 Fin Arrays with Low-Interface Charge Density by Inverse Metal-Assisted Chemical Etching.

β-Ga2O3, with a bandgap of ∼4.6-4.9 eV and readily available bulk substrates, has attracted tremendous interest in the wide bandgap semiconductor community. Producinghigh aspect ratio β-Ga2O3 3D nanostructures without surface damage is crucial for next-generation power electronics. However, most wet etching methods can only achieve very limited aspect ratios, while dry etch usually damages the surface due to high energy ions. In this work, we demonstrate the formation of β-Ga2O3 fin arrays on a (010) β-Ga2O3 substrate by metal-assisted chemical etching (MacEtch) withhigh aspect ratio and sidewall surfaces with excellent quality. The etching was found to be strongly crystal orientation dependent, and three kinds of vertical structures were formed after MacEtch. The Schottky barrier height (SBH) between Pt and various MacEtch-produced β-Ga2O3 surfaces and sidewalls was found to decrease as the aspect ratio of the β-Ga2O3 vertical structure increased. This could be attributed to the different amount of oxygen lost at the surface after etching, as indicated by the XPS and TEM examination. Very little hysteresis was observed in the capacitance-voltage characteristics for the 3D Pt/Al2O3/β-Ga2O3 MOS capacitor structures, and the extracted interface trap density was as small as 2.73 × 1011 cm-2 eV-1, comparable to or lower than that for unetched planar β-Ga2O3 surfaces.

Co-Planar Nano-Resistor Devices

Nano-resistors made from the breakdown of a MOS capacitor with a metal oxide high-k gate dielectric layer have been reported previously [1-3]. The high-k dielectric surrounded nano-resistor structure has many interesting properties suitable for electronic and optoelectronic devices. The material and fabrication process of the nano-resistor device are completely IC compatible. Therefore, the cost of the device can be very low. The nano-resistor structure can be used as diodes or antifues in low- or medium-power logic and memory ICs [4]. Separately, when a voltage is applied through the nano-resistor, light can be emitted from the thermal excitation process [1-3]. This kind of device is named the solid state incandescent light emitting device (SSI-LED) because the light spectrum covers the whole visible and part of the near IR wavelength range with the peak located in the red light region. The light is located in the warm white light region of the CIE chart with a large CCT of above 2,500K and a high CRI of > 95. Similar to the light of the conventional incandescent light bulb, the SSI-LED is suitable for the lighting purpose. In addition, the broadband light can be narrowed down to near the 850 nm wavelength by adding a thin film filter [5,6]. When used in combination with the proper waveguide and modulation units, the SSI-LED can be a light source for the on-chip optical interconnect. Nano-resistors reported in the literature are made from the vertical MOS capacitor structure, as shown in Figure 1(a). Conductive paths are formed from the breakdown of the gate dielectric film due to the large electric field between the top and bottom electrodes. Since all nano-resistor devices are formed on the same wafer sharing the common bottom electrode, electrical interferences or crosstalks among adjacent devices are unavoidable. In this paper, a new type of co-planar nano-resistor structure formed from the MOS capacitor with both electrodes located on the same side of the wafer, as shown in Fig. 1(b), is introduced. The gate dielectric layer is broken from the application of an electric field between the two electrodes. Different nano-resistor devices can be formed individually on the same substrate. When properly isolated, the nano-resistor device can be operated without being interfered by surrounding devices. Then, a large array of devices can be fabricated and operated for various applications. Figure 2 shows breakdown curves of the conventional vertical (control) and the new co-planar structured samples. Nano-resistors are formed in the similar way. Figure 3 shows an array of co-planar nano-resistor devices fabricated on the Si wafer. In this paper, we will describe the fabrication process of the co-planar nano-resistor device. Electrical and optical characteristics of the device will be shown and discussed. Possible applications of this kind of device will also be discussed. [1] Y. Kuo and C.-C. Lin, APL, 102, 031117 (2013). [2] Y. Kuo and C.-C. Lin, SSE, 89, 120 (2013). [3] Y. Kuo, IEEE TED, 62, 3536 (2015). [4] Y. Kuo, ECS Trans. 69(12) 23 (2015). [5] S. Radovanovic, et al, High-Speed Photodiodes Standard CMOS Technol., p. 24 (2006). [6] S. Zhang and Y. Kuo, ECS JSS, 6 Q39 (2017). Figure 1

Substrate Effect on Light Emission of SSI-LEDs

A new type of solid-state incandescent light emitting device (SSI-LED) that emitted broad-band warm white light has been reported recently [1-4]. This kind of device is made from a simple MOS capacitor structure composed a high-k gate dielectric on p-type Si substrate [1-4]. The light emission principle is the thermal excitation of nano-sized conductive paths, i.e., nano-resistors, formed from the dielectric breakdown of the MOS capacitor upon the pass of a large current [4]. Since the whole device is made with IC-compatible materials and processes, one of the possible applications is the on-chip optical interconnect [5]. It also shows antifuse- and diode-like characteristics which are suitable for IC and other applications [6,7]. Since the nano-resistors are formed from the breakdown of the MOS structure, all materials in the current path, i.e., including the dopant concentration of the substrate, can contribute to the light emission process [8]. In this paper, authors investigated the Si substrate effect on light emission of the SSI-LED. SSI-LEDs made of p-type <100> Si wafers of two different dopant concentrations, i.e., p (~1015 cm-3) and p + (~1017 cm-3), were fabricated. The Zr-doped HfO2 (ZrHfO) dielectric film was sputtered from a Zr/Hf (12/88 wt. %) target on the substrate in Ar/O2 (1:1) at 5 mTorr and 60 W for 12 min. Then, the sample was annealed at 800°C in N2 for 3 min. Subsequently, an ITO film was deposited on top of the high-k stack and wet-etched into 300 µm-diameter dots as the gate electrodes. An Al film was deposited on the backside of the wafer to form the ohmic contact. Finally, the sample was annealed at 400°C in forming gas for 5 min. The complete SSI-LED was stressed at a gate voltage (Vg ) of -25 V for the light emission characteristics. Figure 1 are top-view photos of light emission from SSI-LEDs made on (a) p and (b) p+ Si wafers. Both photos showed that the light was emitted from many discrete bright dots evenly distributed across the gate electrode. Each dot corresponds to a nano-resistor. The p+ sample contains many more dots than the p sample does. The bright dots were almost distributed everywhere across gate electrode of the p+ substrate device. This is because the breakdown strength decreases markedly with the increase of the substrate doping concentration [8]. Therefore, under the same Vg stress, it is easier to form more conductive paths in the gate dielectric thin film in the p+ sample than in the p sample. The light emission photo of the former looks brighter than that of the latter. Figure 2 shows the light emission spectra of the p and p+ samples. Both spectra cover the same wavelength range including the visible and some of the near IR lights. The p+ sample has a much higher light intensity than the p sample has, which is consistent with the observation of Fig. 1. The more nano-resistors are formed, the stronger the light is emitted from the SSI-LED. The peak wavelengths of both devices are very close, i.e., 700 nm for the p substrate device and 707 nm for the p+ substrate device. The CIE color coordinates, color correlated temperature (CCT), and color rendering index (CRI) values were calculated and listed in Table 1. Both samples have similar CIE characteristics, which indicates the similar conductive path properties. In summary, the light emission characteristics of the SSI-LED is influenced by the dopant concentration of the Si wafer, which affects the breakdown of the MOS capacitor and the formation of nano-resistors. [1] Y. Kuo et al, APL, 102, 031117 (2013). [2] Y. Kuo et al, ESSL, 2, Q59 (2013). [3] Y. Kuo et al, SSE, 89, 120 (2013). [4] C.-C. Lin et al, APL, 106, 121107 (2015). [5] S. Zhang et al, ECS JSS, 6, Q39 (2017). [6] Y. Kuo, ECST, 69, 23 (2015). [7] Y. Kuo, ECST, 67, 183 (2015). [8] C. Osburn et al, JES, 119, 597 (1972). Figure 1

(Invited) Surface Passivation of High-k Dielectric Materials on Diamond Thin Films

Single-crystalline CVD diamond films have excellent electrical and material properties with potential in high power, high voltage and high frequency applications that are out of reach for conventional semiconductor materials. For realization of efficient devices (e.g. MOSFET), finding a suitable dielectric is essential to improve the reliability and electrical performance of devices. In the current study, we present results from surface passivation studies by high-k dielectric materials such as aluminum oxide and hafnium oxide deposited by ALD on intrinsic and boron doped diamond substrates. The hole transport properties in the intrinsic diamond films were evaluated and compared to unpassivated films using the lateral time-of-flight technique. The MOS capacitor structure, which forms the basic building block of the MOSFET, is discussed.

(Invited) Surface Passivation of High-k Dielectric Materials on Diamond Thin Films

Single-crystalline CVD diamond films have excellent electrical and material properties with potential applications in high power, high voltage and high frequency applications that are out of reach for conventional semiconductor materials. For realization of efficient devices (e.g. MOSFET), finding a suitable dielectric is essential to improve the reliability and electrical performance of devices. In the current study, we present results from surface passivation studies by high-k dielectric materials such as aluminum oxide and hafnium oxide deposited by ALD on intrinsic and boron doped diamond substrates. The hole transport properties in the intrinsic diamond films were evaluated and compared to unpassivated films using the lateral time-of-flight technique. Also, for the advancement of diamond-based electronic devices, the fabrication of MOSFET is crucial as this device finds applications in numerous fields of power electronics and high frequency systems. The MOS capacitor structure which forms the basic building block of the MOSFET is discussed. Inversion phenomenon crucial for the operation of MOSFET observed for the first time in boron doped diamond will be discussed.

Inversion in Metal–Oxide–Semiconductor Capacitors on Boron-Doped Diamond

For the advancement of diamond-based electronic devices, the fabrication of metal-oxide-semiconductor field-effect transistors (MOSFETs) is crucial, as this device finds applications in numerous fields of power electronics and high-frequency systems. The MOS capacitor forms the basic building block of the MOSFET. In this letter, we describe planar MOS capacitor structures fabricated with atomic layer deposited aluminum oxide as the dielectric on oxygen-terminated boron-doped diamond substrates with different doping levels. Using capacitance-voltage measurements, we have, for the first time, observed inversion behavior in MOS structures on boron-doped diamond, with a doping concentration of 4.1 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">19</sup> /cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> .

Ultra-Thin, High Quality HfO2 on Strained-Ge MOS Capacitors with Low Leakage Current

Strained-Ge is a promising channel material for future CMOS nodes due to its very high hole mobility [1] and compatibility with existing processes. In comparison to Si, high quality dielectric interfaces for Ge are challenging due to the lack of an ideal native oxide. In this work, for the first time, we show an extremely-scaled (EOT < 5 Å), high quality dielectric on s-Ge. CV measurements of a MOS capacitor structure show areal capacitance scaling, little hysteresis, and low gate leakage current (< 0.2 A/cm2).The epitaxial structure (shown in Fig. 1(a)) was grown by low-pressure CVD, and the s-Ge layer is compressively strained (2.3% biaxial) due to the lattice mismatch with the relaxed Si0.55Ge0.45 virtual substrate. The epitaxial wafer was cleaved into pieces, and a 5-minute 1:10 (HCl:H2O) clean was performed prior to atomic layer deposition (ALD) of 1 minute O3/~3 nm HfO2 (both at 250 °C), followed by ~10 nm of TiN at 300 °C. After ALD, Al contacts were sputtered and patterned followed by a 30-minute forming gas anneal at 450 °C. The final MOS capacitor structure (Fig. 1(a)) reflects the loss in the s-Ge due to the HCl clean and O3 oxidation.CV measurements of a 100×100 µm MOS capacitor show a CET of 8.6 Å (Fig. 2). Large frequency dispersion exists for frequencies > 50 kHz due to large series resistance likely caused by a 500 meV valence band offset [2] between s-Ge and Si0.55Ge0.45 (Fig. 1(b)). The IV measurements (Fig. 3) show small gate leakage current (< 0.2 A/cm2), which translates to IG < 20 pA/µm for LG = 10 nm, well below ITRS requirements [3].Quasistatic one-dimensional self-consistent coupled Poisson-Schrödinger electrostatic simulations were performed in order to extract EOT. A strain-dependent 6×6 k∙p Hamiltonian (with deformation potentials from [2]) was used to calculate hole quantization in the s-Ge layer. In accordance with [4], a 2.1 eV valence band offset between Ge and GeOx was used in the simulations (Fig. 1(b)). The 500 meV valence band offset between between s-Ge and Si0.55Ge0.45creates a deep quantum well confining most of the holes in the s-Ge layer.Fig. 5 shows the 10 kHz experimental CV in addition to simulated quasistatic CV curves for structures with varying EOT. The mismatch of the simulated and experimental curves in strong hole accumulation is due to both a large series resistance (Rs ~ 0.1 Ω∙cm2) and gate leakage, which causes a sizable error when transforming the measured impedance to a two-element parallel capacitance CP , parallel conductance GP circuit model [5]. A circuit model (inset Fig. 6) incorporating parasitic gate tunneling conductance Gt and series resistance Rs is applied to an ideal simulated CV in order to recover the measured CV result, yielding an extracted EOT of 4.9 Å (Fig. 6). This is the smallest known EOT for a high quality dielectric on s-Ge published to date. Other recent results include a 7-Å EOT on s-Ge [6], and an 8-Å CET on unstrained Ge [7].

Electrical characterization of thulium silicate interfacial layers for integration in high-k/metal gate CMOS technology

This work presents a characterization of the electrical properties of thulium silicate thin films, within the scope of a possible application as IL (interfacial layer) in scaled high-k/metal gate CMOS technology. Silicate formation is investigated over a wide temperature range (500–900°C) through integration in MOS capacitor structures and analysis of the resulting electrical properties. The results are compared to those obtained from equivalent devices integrating lanthanum silicate interfacial layers. The thulium silicate IL is formed through a gate-last CMOS-compatible process flow, providing IL EOT of 0.1–0.3nm at low formation temperature and interface state density at flatband condition below 2×1011cm−2eV−1. The effects of a possible integration in a gate-first process flow with a maximum thermal budget of 1000°C are also evaluated, achieving an IL EOT of 0.2–0.5nm, an interface state density at flatband condition ∼1×1011cm−2eV−1 and a reduction in gate leakage current density of one order of magnitude compared to the same stack without IL.

Influence of O2 flow rate on HfO2 gate dielectrics for back-gated graphene transistors

HfO2 thin films deposited on Si substrate using electron beam evaporation, are evaluated for back-gated graphene transistors. The amount of O2 flow rate, during evaporation is optimized for 35 nm thick HfO2 films, to achieve the best optical, chemical and electrical properties. It has been observed that with increasing oxygen flow rate, thickness of the films increased and refractive index decreased due to increase in porosity resulting from the scattering of the evaporant. The films deposited at low O2 flow rates (1 and 3 SCCM) show better optical and compositional properties. The effects of post-deposition annealing and post-metallization annealing in forming gas ambience (FGA) on the optical and electrical properties of the films have been analyzed. The film deposited at 3 SCCM O2 flow rate shows the best properties as measured on MOS capacitors. To evaluate the performance of device properties, back-gated bilayer graphene transistors on HfO2 films deposited at two O2 flow rates of 3 and 20 SCCM have been fabricated and characterized. The transistor with HfO2 film deposited at 3 SCCM O2 flow rate shows better electrical properties consistent with the observations on MOS capacitor structures. This suggests that an optimum oxygen pressure is necessary to get good quality films for high performance devices.

Fabrication and characterization of gridded Pt/SiO2/Si MOS structure for hydrogen and hydrogen sulphide sensing

A gridded gate Pt/SiO2/Si MOS capacitor has been fabricated for detection of Hydrogen (H2) and Hydrogen Sulphide (H2S) gases. The MOS device was fabricated on P-type Si <100> (1–6 Ω cm) wafer with thermal oxide layer of thickness about 100 Å, whereas, Platinum (Pt) gate of ∼350 Å was deposited by thermal evaporation technique. The C–V (capacitance vs voltage) and G–V (conductance vs voltage) measurements have been performed for the evaluation of gas sensing behavior of fabricated MOS capacitor structure in H2 (250–4000 ppm) and H2S (1000–6000 ppm) gases at both room and 120 °C temperatures, in a closed chamber in air atmosphere. It has been observed that the value of capacitance decreases with increase in gas concentration. The fabricated MOS capacitor sensor has shown better sensitivity towards H2 (88.6%) at room temperature (∼25 °C) as compared to (∼45%) at 120 °C. Scanning electron microscopy (SEM) and Atomic force microscopy (AFM) studies have revealed the porous nature of the deposited metal film. The side wall diffusion, spillover of Hydrogen into oxide layer, increase in fixed oxide charge density, increase in surface area caused by gridded structure, the formation of dipole layer and change in interface state density on gas exposure, may be the mechanisms of gas sensing for improved sensitivity of the fabricated MOS device.

A study of nitrogen behavior in the formation of Ta/TaN and Ti/TaN alloyed metal electrodes on SiO2 and HfO2 dielectrics

We studied Ta, TaN, and sub-stoichiometric TaNx electrodes (obtained by nitrogen redistribution in Ta/TaN or Ti/TaN bilayers) deposited on thermal SiO2 and HfO2/IL (0.8 nm SiO2 IL, i.e., interlayer) stacks. Effective work-functions (WF) were extracted on MOS capacitor structures on SiO2 bevelled insulator of 4.2 eV for pure Ta, 4.6 eV for TaN, and 4.3 eV for sub-stoichiometric TaNx. This intermediate WF value is explained by TaN nitrogen redistribution with reactive Ta or Ti elements shifting the gate work-function toward the Si conduction band. The same electrodes deposited on an HfO2/IL dielectric showed different behavior: First, the Ta/HfO2/IL stack shows a +200 meV WF increase (towards the Si valence band) compared to the SiO2 dielectric stack. This increase is explained by the well-known HfO2/IL dipole formation. Second, in contrast to electrodes deposited on SiO2, sub-stoichiometric TaNx/HfO2 is found to have a lower WF (4.3 eV), than pure Ta on HfO2 (4.4 eV). This inversion in work-function behavior measured on SiO2 vs. HfO2 is explained by the nitrogen redistribution in Ta/TaN bilayer together with diffusion of nitrogen through the HfO2 layer, leading to Si-N formation which prevents dipole formation at the HfO2/IL interface.

Post Deposition Annealing Temperature Effect on White-Light Emitting of WOx Thin Film Stack on Si

Post Deposition Annealing Temperature Effect on White-Light Emitting of WOx Thin Film Stack on Si

White-Light Emission from Amorphous ZrHfO Thin Film Dielectrics with and without Embedded Nanocrystalline CdSe Dots

White-Light Emission from Amorphous ZrHfO Thin Film Dielectrics with and without Embedded Nanocrystalline CdSe Dots

High Temperature Hydrogen Sensor Based on Silicon Carbide (SiC) MOS Capacitor Structure

MOS capacitor devices based on silicon carbide (SiC) are largely used as hydrogen detectors in high temperature and chemically reactive environments. A SiC MOS capacitor structure used as hydrogen sensor is analyzed by extensive simulations. The sensitivity to hydrogen detection, stability to temperature variation and dependence on interface states concentration are evaluated. The effects of structure parameters on sensors performance are also investigated. Results show that the oxide layer type and thickness and the SiC polytype have a significant influence on the detectors performance. The proposed optimum structure for high temperature hydrogen detection is based on 3C-SiC substrate and 10nm TiO2 layer. In accordance with the simulations results, three types of masks are designed for the fabrication of SiC MOS capacitor structures.

Effect of nitrogen containing plasma on interface properties of sputtered ZrO2 thin films on silicon

The present paper deals with the electrical characterization of sputtered ZrO2/Si interface deposited in N2 containing plasma. Incorporation of nitrogen in the sputter deposited films was confirmed by glancing angle X-Ray diffraction measurement. MOS C–V and I–V techniques were used for interface characterization. Nitrogen incorporated ZrO2 MOS capacitors exhibited higher breakdown voltage and lower leakage current than structures having ZrO2 dielectric films sputtered in pure argon atmosphere. Different device parameters such as flat band voltage, leakage current, breakdown voltage, charge defects were extracted and compared with and without nitrogen incorporated ZrO2/Si MOS capacitor structures. The effect of post deposition annealing on the electrical behavior of ZrO2/Si interface was also investigated.

Influence of the Surface Pretreatment on the Electrical Properties of MgO and Al2O3 Gate Stacks grown by MBE

For CMOS devices, the interface between the dielectric and the semiconductor is of crucial importance for the electrical properties. This paper is devoted to examining the role of different substrate preparation procedures on the interface properties. After the surface treatment 5 nm amorphous oxide films were deposited by molecular beam epitaxy (MBE). MgO on Si was chosen as our main model system. Additionally, a higher k dielectric, Al2O3, was also studied. The electrical properties were investigated through measurements of MOS capacitor structures. Mainly capacitance density measurements as a function of voltage C-V were performed and analysed. Moreover, post-metal annealing experiments were performed in order to change the interface configuration and to optimize the electrical properties. The results demonstrate that the interface properties can be well controlled by the pretreatment of the substrates. Surprisingly it was also found that an identical surface pretreatment – despite the different dielectrics – induced a systematic, reproducible and substantial VFB shift of the C-V curves while most other parameters remain unaffected. This opens additional possibilities to fine-tune the flat-band voltage in such high-k transistors.

(Invited) Can Metal/Al2O3/In0.53Ga0.47As/InP MOSCAP Properties Translate to Metal/Al2O3/In0.53Ga0.47As/InP MOSFET Characteristics

In this paper we present the electrical characteristics of Metal/Al2O3/In0.53Ga0.47As/InP MOS capacitor (MOSCAP) structures formed using a relatively straightforward capacitor process flow and for MOSCAPs which experience the full process flow of an In0.53Ga0.47As n channel MOSFET. From analysis of the capacitance-voltage response over a range of ac signal frequencies fixed oxide charge densities and interface state concentrations are determined for the MOSCAP structures and the impact of forming gas annealing on oxide and interface state densities is presented. The MOSCAP results are compared to the properties of fully processed metal/Al2O3/In0.53Ga0.47As/InP n channel MOSFETs, and the results indicate that the findings from the MOSCAPS do translate to the measured InGaAs MOSFET characteristics.