Modulo 2n Research Articles

FPGA Implementation of a Novel Multifunction Modulo (2n ± 1) Multiplier Using Radix-4 Booth Encoding Scheme

The residue number system is widely used in applications such as communication systems, cryptography, digital filters, digital signal processors, fault-tolerant detection, and so on. This paper proposes a multifunction modulo (2n ± 1) multiplier based on the radix-4 Booth encoding scheme that can operate both modulo (2n − 1) and modulo (2n + 1) multipliers using the same hardware structure with only one control signal. A novel modulo (2n ± 1) multiplier based on radix-4 Booth encoding is proposed that can achieve superior performance, with low power, fast operation, high area efficiency, and low area-delay product (ADP) and power-delay product (PDP) compared with similar modified Booth-encoding methods. In addition, by integrating the separate modulo functions of the modulo (2n − 1) multiplier and modulo (2n + 1) multiplier into a single multifunction modulo (2n ± 1) multiplier, the proposed method can save up to 52.59% (n = 16) of hardware area, up to 5.45% (n = 32) of delay time, up to 49.05% (n = 16) of dynamic power, up to 50.92% (n = 32) of ADP, and up to 50.02% (n = 32) of PDP compared with the original separate circuits merged together. Furthermore, the operation ranges of the multiplicand and multiplier of the proposed modulo (2n + 1) multiplier and modulo (2n − 1) multiplier are {0, 2n + 1} and {0, 2n}, respectively, which are wider than for other reported hardware structures. The hardware area, power consumption, and delay time are simulated and verified using Verilog HDL and Xilinx FPGA (Field Programmable Gate Array) Vivado tools. The Xilinx Artix-7 XC7A35T-CSG324-1 FPGA chipset is adopted in the proposed work.

On the modulo 2n+1 addition and subtraction for weighted operands

In this paper, investigation is performed on the design of efficient modulo 2n+1 adders, subtractors and add/subtract units for weighted operands. The existing modulo 2n+1 adder, subtractor architectures are reviewed and compared. A new efficient modulo 2n+1 adder architecture for weighted operands is also presented. The proposed modulo 2n+1 adders and one of the existing most efficient modulo 2n+1 subtractors are combined into a modulo 2n+1 add/subtract unit. The proposed modulo 2n+1 add/subtract units exhibit decreased area and power complexity when compared to existing ones.

Efficient Modulo Multiplier

The paper presents the methodology to compute modulo multiplication with the moduli set 2n, 2n−1, 2n+1. In addition to this, designs of the modulo multipliers, namely 2n, 2n−1, and 2n+1 (with n = 4, 8, and 16), have been proposed which are based on half adders, full adders, 4:3 compressor, 7:3 compressor, and the multi-column compressor namely 5,5:4. The gate level design of 4:3 compressor is carried out by solving the truth table using the K-map reduction. To verify the functionalities we have implemented the proposed modulo multipliers using VHDL coding in Xilinx 14.2 design suite. Simulation using Virtex-6 device has been performed to estimate delay, power consumption, and power-delay product (PDP). Moreover, the modulo multipliers are simulated in Cadence RC compiler using 0.18 µm technology to estimate the area. One of the major contributions to the arts of this work is in the partial product reduction stage which utilizes the multi-column 5,5:4 compressor to reduce power and area. The modulo 2n−1 multiplier of operand size 4-bit shows an improvement of 66.34% in terms of area over the best-reported paper. On the other hand, the modulo 2n+1 multiplier of operand size 4-bit shows an improvement of 58.59% terms of in area and the same of operand size 8-bit shows an improvement of 22.72% over the best-reported paper. The proposed algorithms of moduli multiplication are applicable to Booth multiplication of signed numbers.

Can the radial number of vortex modes control the orbital angular momentum?

In general, a standard Laguerre–Gauss (LG) beam, whose state is given by two quantum numbers (n, 𝓁): the radial number n and the azimuthal number 𝓁 (or the topological charge (TС) of the vortex carried by the LG beam), is unstable with respect to weak perturbations. This is not difficult to see if we decompose the complex amplitude of the LG beam in terms of Hermite–Gauss modes (HG), with the total number of HG modes being equal to N = 2n +𝓁 + 1. If we now slightly change the amplitudes and phases of each HG mode, then the structure of the LG beam radically changes. Such a combination of modes is called a structured LG beam (sLG), which can carry large additional arrays of information embedded in the sLG beam by encoding the amplitudes and phases of the HG modes (excitation of modes). But as soon as a perturbation is inserted into the LG beam, its orbital angular momentum (OAM) can change dramatically in such a way that the value of the OAM changes in the interval (–𝓁, 𝓁), and the total TC – in the interval (–2n – 𝓁, 2n + 𝓁). At n = 0, the OAM changes smoothly in the interval (–𝓁, 𝓁), however it is worth "turning on" the radial number n, as the OAM oscillations occur. The number of minima (maxima) of the oscillations is equal to the radial number n in the interval θ = (0, π) and θ = (π, 2π), with their amplitude nonlinearly depending on the difference 𝓁 – n, except for the point θ = π, where the structured beam becomes degenerate. If 𝓁 = 0, then the OAM is zero, so that in the sLG beam structure, we observe either a symmetrical array of vortices with opposite-sign TCs or a pattern of edge dislocations, the number of which is equal to the radial number n. We also found that, despite the fast oscillations of the OAM, the absolute value of the total TC of the sLG beam does not change with variation of both the amplitude ε and phase θ parameters, but depends solely on the initial state (n, 𝓁) of the LG beam and modulo (2n + 𝓁).

Area Efficient Diminished 2n-1 Modulo Adder using Parallel Prefix Adder

Residue Number System has to carry free operation and its various applications like digital signal processing, multimedia, security purpose, and medical perception. Removes of the redundant logic operation require the group carry selection logic which is dependent on Parallel Prefix Adder design. Therefore the logic operation of the preprocessing unit of PPA is simplified form to save logic resources. This modified parallel prefix adder consumes less area as compared to the existing design. In this paper, we propose the parallel architecture based on a parallel prefix tree is helpful for computation at higher speed operation. The reported design consumes 24.1% more area and 26.4% more power compare to THE proposed parallel prefix adder design. The proposed PPA design using modified carry computation algorithm and reported design used diminished-1 modulo 2n+1 adder structure is presented. A presented modulo adder design using the proposed parallel prefix adder and improved carry computation used in the previously proposed design. The proposed diminished-1 modulo (2n +1) adder design shows a 24.5% saving in area-delay-product (ADP).

Maximums of the Additive Differential Probability of Exclusive-Or

At FSE 2004, Lipmaa et al. studied the additive differential probability adp⊕(α,β → γ) of exclusive-or where differences α,β,γ ∈ Fn2 are expressed using addition modulo 2n. This probability is used in the analysis of symmetric-key primitives that combine XOR and modular addition, such as the increasingly popular Addition-Rotation-XOR (ARX) constructions. The focus of this paper is on maximal differentials, which are helpful when constructing differential trails. We provide the missing proof for Theorem 3 of the FSE 2004 paper, which states that maxα,βadp⊕(α,β → γ) = adp⊕(0,γ → γ) for all γ. Furthermore, we prove that there always exist either two or eight distinct pairs α,β such that adp⊕( α,β → γ) = adp⊕(0,γ → γ), and we obtain recurrence formulas for calculating adp⊕. To gain insight into the range of possible differential probabilities, we also study other properties such as the minimum value of adp⊕(0,γ → γ), and we find all γ that satisfy this minimum value.

ИССЛЕДОВАНИЕ ВОЗМОЖНОСТИ ПРИМЕНЕНИЯ ЛИНЕЙНОГО АНАЛИЗА К ARX АЛГОРИТМАМ СТОХАСТИЧЕСКОГО ПРЕОБРАЗОВАНИЯ ДАННЫХ В ЗАВИСИМОСТИ ОТ ФУНКЦИИ СМЕШЕНИЯ С РАУНДОВЫМ КЛЮЧОМ

ARX stochastic algorithms are a promising solution in the development of unpredictable pseudo- random number generators for low-resource systems. The ease of implementation of their round operations, as well as their high energy efficiency, make the choice of such algorithms attractive for ensuring the confidentiality of information. Existing studies on the possibility of applying linear analysis to ARX stochastic algorithms use imprecise linear approximations of round functions. The key idea of linear analysis is the use of linear statistical analogs of non-linear functions. Linear approximations are used to express the inputs of the stochastic transformation algorithm by its outputs as a linear function. The resulting linear function is true with a certain probability, which depends on the probability of fulfilling the used linear approximations. The only non-linear operation in ARX algorithms is addition modulo 2n. In this paper we study the limitations of the applicability of the linear analysis to ARX stochastic transformation algorithms. The study is carried out for various cases of the implementation of round key addition: the use of the addition modulo 2n, the addition modulo 2, and the cyclic shift. For ARX stochastic transformation algorithms, using addition modulo 2n or addition modulo 2 as a round key mix operation, estimates are obtained for the number of addition operations modulo 2n needed to ensure their stability to linear analysis.

Quantum Modular Adder over GF(2n − 1) without Saving the Final Carry

Addition is the most basic operation of computing based on a bit system. There are various addition algorithms considering multiple number systems and hardware, and studies for a more efficient addition are still ongoing. Quantum computing based on qubits as the information unit asks for the design of a new addition because it is, physically, wholly different from the existing frequency-based computing in which the minimum information unit is a bit. In this paper, we propose an efficient quantum circuit of modular addition, which reduces the number of gates and the depth. The proposed modular addition is for the Galois Field GF(2n−1), which is important as a finite field basis in various domains, such as cryptography. Its design principle was from the ripple carry addition (RCA) algorithm, which is the most widely used in existing computers. However, unlike conventional RCA, the storage of the final carry is not needed due to modifying existing diminished-1 modulo 2n−1 adders. Our proposed adder can produce modulo sum within the range 0,2n−2 by fewer qubits and less depth. For comparison, we analyzed the proposed quantum addition circuit over GF(2n−1) and the previous quantum modular addition circuit for the performance of the number of qubits, the number of gates, and the depth, and simulated it with IBM’s simulator ProjectQ.

IMPLEMENTATION OF REVERSIBLE CIRCUITBASED KOGGE STONE PREFIX MODULO ADDER

For high speed computing, the need for an efficient adder is essential.In addition module, carry propagation becomes the bottleneck problem which increases the delay. To avoid thisproblem, arithmetic functions can be implemented using Residue Number System (RNS) which provides carry free and parallel operation. Though RNS performs several moduli in parallel form, it consumes more time and has high power dissipation.Reversible logic is a very promising alternative to conventional logic system forreducing the power dissipation.Reversible logic is the memory less logic which is used for ultra-low power reliable circuits.In this paper the Kogge stone prefix adder architecture is used which is considered as fast adder. The adder architecture is used to perform modulo 2n -1 operation and is implemented using reversible circuits. This method offers high speed computing and also minimum power dissipation. The proposed method is simulated using Xilinx 12.4 ISE and the functions are evaluated using MODELSIM 6.3c.

Area and power efficient hard multiple generator for radix-8 modulo 2n − 1 multiplier

In this paper, we introduce an area and power efficient algorithm to design a hard multiple generator for radix-8 modulo 2n − 1 multiplier, which is based on parallel prefix computation of carry propagate. Only odd carry is used to generate hard multiple bits. The proposed architecture uses ⌈log2n⌉-2 prefix level with n2 prefix operators. The Post-synthesis result of proposed architecture shows 27.91%–36.89%, 9.64%–22.45% and 0.02%–88.62% of saving in area, power and PDP, respectively while post-layout result shows 27.66%–36.88%, 14.45%–33.53% and 11.40%–81.11% of saving in area, power and PDP, respectively.

Perspective and Opportunities of Modulo 2n−1 Multipliers in Residue Number System: A Review

Modulo multiplier has been attracting considerable attention as one of the essential components of residue number system (RNS)-based computational circuits. This paper contributes a comprehensive review in the design of modulo [Formula: see text] multipliers for the first time. The modulo multipliers can be implemented using ROM (look-up-table) as well as VLSI components (memoryless); however, the former is preferable for lower word-length and later for larger word-length. The modular and parallelism properties of RNS are used to improve the performance of memoryless multipliers. Moreover, a Booth-encoding algorithm is used to speed-up the multipliers. Also, an advanced modulo [Formula: see text] multiplier based on redundant RNS (RRNS) could be further chosen for very high dynamic range. These perspectives of modulo [Formula: see text] multipliers have been extensively studied for recent state-of-the-art and analyzed using Synopsis design compiler tool.

Implementation of High Speed Modulo (2 +1) Multiplier for IDEA Cipher

Abstract In this brief a new modulo 2n+1 multiplier is proposed for IDEA block cipher. A total of (n+1) partial products including a constant correction term are added using tree of Carry save adder with end around complemented carry followed by modulo adder. Wallace tree multiplier is adopted in order to improve the accumulation of partial products. Proposed modulo multiplier is compared with the other modulo multipliers available in the literature for IDEA block cipher. The VLSI implementation of proposed multiplier utilizing carry save tree architecture achieves (30 to 35%) improvement in the delay whereas Wallace tree architecture achieves (32 to 41.5%).

On the Diminished-1 Modulo 2n+1 Addition and Subtraction

In this work, the design of the diminished-1 modulo [Formula: see text] adders, subtractors and adders/subtractors are examined. Some of the existing modulo [Formula: see text] adders, subtractors and adder/subtractors are redesigned and improved. Compared to other existing implementations, the proposed subtractor and adder/subtractors offer reduced area complexity and lower power consumption, while operating at the same speed. All the considered architectures are modified parallel-prefix adders with fast input carry processing. The totally parallel-prefix and carry look ahead implementation of the proposed arithmetic units are also discussed.

High‐throughput and flexible ASIC implementations of SIMON and SPECK lightweight block ciphers

SummaryIn this paper, high‐throughput and flexible hardware implementations of the SIMON and SPECK lightweight block ciphers are presented. The most complex block in the SPECK algorithm is addition modulo 2n, where n is word size (half of the input data). In the proposed structure of modular adder, we used the Sklansky adder, which is an efficient parallel prefix adder with low critical path delay and suitable hardware resources. In the SIMON block cipher, to reduce critical path delay, we use a tree structure for implementation of XOR operations. In addition, we proposed flexible structures that can perform various configurations of the SIMON and SPECK ciphers to support variable key sizes (128, 144, 192, and 256 bits) and block sizes (64, 96, and 128 bits). Therefore, the flexible architectures provide versatile implementations with adaptive security level and the ability of encryption of longer messages based on variable key size and variable block size. Implementation results of the proposed structures in 180 nm CMOS technology for different key and block sizes are achieved. The results show that the proposed structures have better critical path delay compared with other's related works.

A New Method for Differential Cryptanalysis on Addition on Residue Class Ring Z/2nZ

In the paper, we present a new method to study the differential properties of addition modulo 2n using the formulas of coefficients of sum of 2-adic integers.

On the order of odd integers modulo 2n

In this paper, we investigate the order of odd integers of the forms 2ju + 1 and 2ju+3 modulo 2n, where j is an integer with j ? 2, u is an odd positive integer, and n is an integer with n ? j + 3.

Isomorphic transformation and its application to the modulo (2n + 1) channel for RNS based FIR filter design

In this paper, the implementation of a Finite Impulse Response (FIR) filter in the Residue Number System (RNS), is presented, in which a modulo multiplier based on the isomorphism technique is used to perform multiplication in the (2n + 1) channel. An RNS modular multiplication in the Galois Field GF(2n + 1) is presented in detail in this paper. The multiplication is based on the isomorphic mapping technique adapted to the residue arithmetic. The isomorphic encoder and decoder look-up tables in the GF(28 + 1) are given. An architecture for FIR filter design based on distributed arithmetic for multiplication and accumulation in mentioned (2n + 1) channel is also presented. This architecture is discussed in details and compared with with architecture based on isomorphing technique.

Area-Time-Power Efficient Maximally Redundant Signed-Digit Modulo 2n − 1 Adder and Multiplier

By increasing the length of input operands, standard binary number representation cannot satisfy the need for area-time-power efficient systems due to carry propagation chain problem. Redundant residue number system (RRNS) would be an appropriate solution to this demand as it divides large numbers to smaller ones on which the arithmetic operations could be performed in parallel. Maximally redundant signed-digit RNS (MRSD-RNS) has been recently presented as a low-power RRNS because the addition unit based on this number system consumes the least power among the existing RRNS encodings. In this work, a low-power MRSD-RNS multiplier for modulo 2n− 1 is proposed for the first time. The implementation results based on the TSMC-90 nm CMOS Technology indicate that our proposed design outperforms power, area, power-delay-product and area-delay-product in comparison with the efficient existing RRNS multipliers for the cases in which delay is not a limiting factor. It has also the least delay among the existing high-radix RRNS multipliers. Therefore, the proposed multiplier can meet the strict area-time-energy constraints which can be used as the core of signal processor in many applications.

Application of sequential method for constructing a statistical attack on the LPN-C cipher system over residue ring modulo 2N

LPN-C is one of the first post-quantum symmetric cipher systems, which security relies on the complexity of solving the LPN problem. The original version of the cipher system is defined over the field of two elements, nevertheless it is naturally generalized to the case of an arbitrary finite ring. Usually such generalization associated with the complication of the algebraic structure of underlain object used for construction of a cipher system increases its security to known attacks, however, as shown below, the LPN-C cipher system over a residue ring modulo 2Nrepresents an exception to this rule. In this article, an attack on the LPN-C cipher system over the residue ring modulo 2Nis proposed. The attack is based on recovering the key by sequential solving N systems of linear equations corrupted by noise over the field of order two. It is shown that the proposed attack is significantly more effective in comparison with traditional attacks of the same type based on direct solving these systems using the generalized BKW algorithm. The obtained results indicate that the residue rings modulo 2N, N≥2, are not expedient for constructing LPN-C cipher systems, since this does not lead to significant increasing the security in comparison with 1N= case.

Modulo 2n+1 Multiply and MAC Units Specified for DSPs

Modulo 2n+1 Multiply and MAC Units Specified for DSPs