Area-Time-Power Efficient Maximally Redundant Signed-Digit Modulo 2n − 1 Adder and Multiplier

Abstract

By increasing the length of input operands, standard binary number representation cannot satisfy the need for area-time-power efficient systems due to carry propagation chain problem. Redundant residue number system (RRNS) would be an appropriate solution to this demand as it divides large numbers to smaller ones on which the arithmetic operations could be performed in parallel. Maximally redundant signed-digit RNS (MRSD-RNS) has been recently presented as a low-power RRNS because the addition unit based on this number system consumes the least power among the existing RRNS encodings. In this work, a low-power MRSD-RNS multiplier for modulo 2n− 1 is proposed for the first time. The implementation results based on the TSMC-90 nm CMOS Technology indicate that our proposed design outperforms power, area, power-delay-product and area-delay-product in comparison with the efficient existing RRNS multipliers for the cases in which delay is not a limiting factor. It has also the least delay among the existing high-radix RRNS multipliers. Therefore, the proposed multiplier can meet the strict area-time-energy constraints which can be used as the core of signal processor in many applications.