Modern Field Programmable Gate Arrays Research Articles

Error Detection and Correction in SRAM Emulated TCAMs

Ternary content addressable memories (TCAMs) are widely used in network devices to implement packet classification. They are used, for example, for packet forwarding, for security, and to implement software-defined networks (SDNs). TCAMs are commonly implemented as standalone devices or as an intellectual property block that is integrated on networking application-specific integrated circuits. On the other hand, field-programmable gate arrays (FPGAs) do not include TCAM blocks. However, the flexibility of FPGAs makes them attractive for SDN implementations, and most FPGA vendors provide development kits for SDN. Those need to support TCAM functionality and, therefore, there is a need to emulate TCAMs using the logic blocks available in the FPGA. In recent years, a number of schemes to emulate TCAMs on FPGAs have been proposed. Some of them take advantage of the large number of memory blocks available inside modern FPGAs to use them to implement TCAMs. A problem when using memories is that they can be affected by soft errors that corrupt the stored bits. The memories can be protected with a parity check to detect errors or with an error correction code to correct them, but this requires additional memory bits per word. In this brief, the protection of the memories used to emulate TCAMs is considered. In particular, it is shown that by exploiting the fact that only a subset of the possible memory contents are valid, most single-bit errors can be corrected when the memories are protected with a parity bit.

D-TCAM: A High-Performance Distributed RAM Based TCAM Architecture on FPGAs

Ternary content-addressable memory (TCAM) is a high-speed searching device that searches the entire memory in parallel in deterministic time, unlike random-access memory (RAM), which searches sequentially. A network router classifies and forwards a data packet with the aid of a TCAM that stores the routing data in a table. Field-programmable gate arrays (FPGAs), due to its hardware-like performance and software-like reconfigurability, are widely used in networking systems where TCAM is an essential component. TCAM is not included in modern FPGAs, which leads to the emulation of TCAM using available resources on FPGA. Several emulated TCAM designs are presented but they lack the efficient utilization of FPGA's hardware resources. In this paper, we present a novel TCAM architecture, the distributed RAM based TCAM (D-TCAM), using D-CAM as a building block. One D-CAM block implements a 48-bytes TCAM using 64 lookup tables (LUTs), that is cascaded horizontally and vertically to increase the width and depth of TCAM, respectively. A sample size of 512 x 144 is implemented on Xilinx Virtex-6 FPGA, which reduced the hardware utilization by 60% compared to the state-of-the-art FPGA-based TCAMs. Similarly, by exploiting the LUT-flip-flip (LUT-FF) pair nature of Xilinx FPGAs, the proposed TCAM architecture improves throughput by 58.8% without any additional hardware cost.

Area Optimized Synthesis of Compressor Trees on Xilinx FPGAs Using Generalized Parallel Counters

Early compressor trees based on carry-save adders and single-column parallel counters show good performance in ASIC design, but do not adapt well to modern field-programmable gate arrays (FPGAs). Recently, compressor trees built from generalized parallel counters (GPCs) were synthesized on FPGAs to address this issue. Despite the improved timing performance of GPC-based compressor trees, area reduction is not as significant as delay, and can be further optimized. In this paper, we propose improved GPC mappings as well as new approaches for GPC cascading and binding for Xilinx FPGAs. With these improvements, we develop an integer linear programming (ILP) method for FPGA synthesis of GPC-based compressor trees that supports cascading and binding between GPCs. Experimental results show that the single-cycle compressor trees produced by the proposed ILP can reduce the average area by 42.40% compared with those generated by existing heuristic method, but are 13.16% slower; the pipelined compressor trees produced by the proposed ILP can reduce the average area by 33.43% at the cost of an average 14.35% decrease in maximum clock frequency compared with those obtained by existing heuristic method.

Improved Synthesis of Compressor Trees in High-Level Synthesis for Modern FPGAs

In this paper, an approach to synthesize compressor trees in high-level synthesis is proposed. We target the modern field-programmable gate arrays, which integrate carry chains and support fast ternary adders. Two main improvements are achieved in our approach: 1) based on the proposed modified bitmask analysis, we perform bit-level numerical optimizations to shrink the scale of generated compressor trees and achieve a better area-delay performance; 2) by estimating the arrival time of each multi-input addition operand, we combine the use of generalized parallel counters and ternary adders in compressor trees to further reduce the area while maintaining a similar delay performance. A series of experiments shows that our approach reduces the area significantly while maintaining similar delay performance, as compared to the existing approaches.

Frequency-Domain Power Delivery Network Self-Characterization in FPGAs for Improved System Reliability

Modern field-programmable gate arrays (FPGAs) operate at a core voltage around 1 V and therefore even small voltage fluctuations lead to timing violations and logic errors. The power delivery network (PDN) between the voltage regulator and the FPGA core must be carefully designed to achieve a low output impedance over a broad range of frequencies. Simulation tools are commonly used to estimate the impedance, however, they do not account for aging, component variations, and inaccurate modeling of parasitic elements, all of which lead to PDN design deviation. In this paper, two schemes are presented: first, to extract the dc resistance in the power delivery path, and second, to identify the high impedance frequency band(s) in the PDN. The embedded impedance extraction tool is synthesized within the FPGA load, in coordination with a mixed-signal current-mode dc–dc converter. A new self-calibrated carry-chain-based analog-to-digital converter (CC-ADC) is used for high-speed sampling of the core voltage. The proposed schemes are demonstrated on an Intel Cyclone IV FPGA board. Real-time IR -drop compensation is shown to eliminate logic errors in an finite impulse response filter application. It is also shown that the fail/pass map of a crossbar application matches well with the extracted impedance profile versus voltage and frequency. By modifying the PDN based on the extracted results, the voltage operating range and reliability of the crossbar application are greatly extended.

RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs

As a good tradeoff between central processing unit (CPU) and application specific integrated circuit (ASIC), field-programmable gate array (FPGA) is becoming more widely used in both industry and academia. The increasing complexity and scale of modern FPGA, however, impose great challenges on the FPGA placement and packing problem. In this paper, we propose RippleFPGA to solve the packing and placement simultaneously through a set of novel techniques: 1) smooth stair-step flow; 2) implicit packing similar to ASIC legalization (LG); and 3) two-level detailed placement (DP). To enable the flow, a generic, efficient, and false-alarm-free legality checking method is also proposed. Besides, due to the insufficiency of ASIC-like congestion alleviation methods, some FPGA-routing-architecture-aware optimization techniques are proposed to improve the routability. When evaluated by ISPD 2016 Contest benchmarks, RippleFPGA has 5.1% better routed wirelength and $5.5 {\times }$ speedup compared to all the state-of-the-art FPGA placers.

Fast inference of deep neural networks in FPGAs for particle physics

Recent results at the Large Hadron Collider (LHC) have pointed to enhanced physics capabilities through the improvement of the real-time event processing techniques. Machine learning methods are ubiquitous and have proven to be very powerful in LHC physics, and particle physics as a whole. However, exploration of the use of such techniques in low-latency, low-power FPGA (Field Programmable Gate Array) hardware has only just begun. FPGA-based trigger and data acquisition systems have extremely low, sub-microsecond latency requirements that are unique to particle physics. We present a case study for neural network inference in FPGAs focusing on a classifier for jet substructure which would enable, among many other physics scenarios, searches for new dark sector particles and novel measurements of the Higgs boson. While we focus on a specific example, the lessons are far-reaching. A companion compiler package for this work is developed based on High-Level Synthesis (HLS) called hls4ml to build machine learning models in FPGAs. The use of HLS increases accessibility across a broad user community and allows for a drastic decrease in firmware development time. We map out FPGA resource usage and latency versus neural network hyperparameters to identify the problems in particle physics that would benefit from performing neural network inference with FPGAs. For our example jet substructure model, we fit well within the available resources of modern FPGAs with a latency on the scale of 100 ns.

Automated Synthesis of Streaming Transfer Level Hardware Designs

As modern field-programmable gate arrays (FPGA) enable high computing performance and efficiency, their programming with low-level hardware description languages is time-consuming and remains a major obstacle to their adoption. High-level synthesis compilers are able to produce register-transfer-level (RTL) designs from C/C++ algorithmic descriptions, but despite allowing significant design-time improvements, these tools are not always able to generate hardware designs that compare to handmade RTL designs. In this article, we consider synthesis from an intermediate-level (IL) language that allows the description of algorithmic state machines handling connections between streaming sources and sinks. However, the interconnection of streaming sources and sinks can lead to cyclic combinational relations, resulting in undesirable behaviors or un-synthesizable designs. We propose a functional-level methodology to automate the resolution of such cyclic relations into acyclic combinational functions. The proposed IL synthesis methodology has been applied to the design of pipelined floating-point cores. The results obtained show how the proposed IL methodology can simplify the description of pipelined architectures while enabling performances that are close to those achievable through an RTL design methodology.

UTPlaceF 2.0

Modern field-programmable gate array (FPGA) devices contain complex clock architectures on top of configurable logics. Unlike application specific integrated circuits (ASICs), the physical structure of clock networks in an FPGA is pre-manufactured and cannot be adjusted to different applications. Furthermore, clock routing resources are typically limited for high-utilization designs. Consequently, clock architectures impose extra clock constraints and further complicate physical implementation tasks such as placement. Traditional ASIC placement techniques only optimize conventional design metrics such as wirelength, routability, power, and timing without clock legality consideration. It is imperative to have new techniques to honor clock constraints during placement for FPGAs. In this article, we propose a high-performance FPGA placement engine, UTPlaceF 2.0, that optimizes wirelength and routability while honoring complex clock constraints. Our proposed approaches consist of an iterative minimum-cost-flow-based cell assignment as well as a clock-aware packing for producing clock-legal yet high-quality placement solutions. UTPlaceF 2.0 won first place in the ISPD’17 clock-aware FPGA placement contest organized by Xilinx, outperforming the second- and the third-place winners by 4.0% and 10.0%, respectively, in routed wirelength with competitive runtime, on a set of industry benchmarks.

The Conflicted Usage of RLUTs for Security-Critical Applications on FPGA

Modern field programmable gate arrays (FPGAs) have evolved significantly in recent years and have found applications in various fields like cryptography, defense, aerospace, and many more. The integration of FPGA with highly efficient modules like DSP and block RAMs has increased the performance of FPGA significantly. This paper addresses the lesser explored feature of modern FPGA called as reconfigurable LUT (RLUT) whose content can be updated internally, even during run-time. We describe the basic functionality of RLUT and discuss its potential applications for security from both destructive and constructive point of view, highlighting the conflicted usage of RLUTs. Several use cases exploiting RLUT feature in security-critical scenarios (physical attacks related in particular) are studied in detail. The paper proposes design of stealthy hardware Trojans having zero payload overhead to highlight destructive applications which can be built using hardware Trojans. On the other hand, this paper also highlights several constructive applications based on RLUT features, starting from lightweight side-channel countermeasures to kill switch to prevent the FPGA hardware from environmental hazards and malicious attack attempts.

Optimal Single Constant Multiplication Using Ternary Adders

The single constant coefficient multiplication is a frequently used operation in many numeric algorithms. Extensive previous work is available on how to reduce constant multiplications to additions, subtractions, and bit shifts. However, on previous work, only common two-input adders were used. As modern field-programmable gate arrays (FPGAs) support efficient ternary adders, i.e., adders with three inputs, this brief investigates constant multiplications that are built from ternary adders in an optimal way. The results show that the multiplication with any constant up to 22 bits can be realized by only three ternary adders. Average adder reductions of more than 33% compared to optimal constant multiplication circuits using two-input adders are achieved for coefficient word sizes of more than five bits. Synthesis experiments show FPGA average slice reductions in the order of 25% and a similar or higher speed than their two-input adder counterparts.

Architectural Synthesis of Multi-SIMD Dataflow Accelerators for FPGA

Field Programmable Gate Array (FPGA) boast abundant resources with which to realise high-performance accelerators for computationally demanding operations. Highly efficient accelerators may be automatically derived from Signal Flow Graph (SFG) models by using architectural synthesis techniques, but in practical design scenarios, these currently operate under two important limitations - they cannot efficiently harness the programmable datapath components which make up an increasing proportion of the computational capacity of modern FPGA and they are unable to automatically derive accelerators to meet a prescribed throughput or latency requirement. This paper addresses these limitations. SFG synthesis is enabled which derives software-programmable multicore single-instruction, multiple-data (SIMD) accelerators which, via combined offline characterisation of multicore performance and compile-time program analysis, meet prescribed throughput requirements. The effectiveness of these techniques is demonstrated on tree-search and linear algebraic accelerators for 802.11n WiFi transceivers, an application for which satisfying real-time performance requirements has, to this point, proven challenging for even manually-derived architectures.

Demand side management through home area network systems

The increasing demand for power in the Electrical Power System (EPS) causes a significant increase of power in the daily load curve as well as transmission line overload. The large variability in energy consumption in the EPS combined with unpredictable weather events can lead to a situation in which, to save the stability of the EPS, power limits must be introduced or even industrial customers in a given area have to be disconnected, which causes financial losses. Nowadays, a Transmission System Operator (TSO) is looking for additional solutions to reduce peak power, because existing approaches (mainly building new intervention power units or tariff programs) are not satisfactory due to the high cost of services in combination with an insufficient power reduction effect. The paper presents an approach to reduce peak loads with the use of Home Area Network (HAN) systems installed at residential units. The algorithm of the HAN system, executed by the HAN controller, is modeled using Unified Modeling Language (UML). Then using model transformation techniques, the UML model is translated into Verilog description, and is finally implemented in the Field Programmable Gate Array (FPGA). The advantages of the proposed approach are that with only a small loss of residential user comfort, there is a gain in energy reduction for a relatively small cost, an effective and convenient design of the HAN algorithm, and the flexible maintenance of HAN systems. The latter gain is possible thanks to using modern FPGAs, which allow for dynamic reconfiguration of the HAN controller. It means that a HAN algorithm of a selected user can be exchanged without power interruption of other residential users. Apractical example illustrating the proposed approach and a calculation of the potential gains from its implementation are also presented.

SNAVA—A real-time multi-FPGA multi-model spiking neural network simulation architecture

Spiking Neural Networks (SNN) for Versatile Applications (SNAVA) simulation platform is a scalable and programmable parallel architecture that supports real-time, large-scale, multi-model SNN computation. This parallel architecture is implemented in modern Field-Programmable Gate Arrays (FPGAs) devices to provide high performance execution and flexibility to support large-scale SNN models. Flexibility is defined in terms of programmability, which allows easy synapse and neuron implementation. This has been achieved by using a special-purpose Processing Elements (PEs) for computing SNNs, and analyzing and customizing the instruction set according to the processing needs to achieve maximum performance with minimum resources. The parallel architecture is interfaced with customized Graphical User Interfaces (GUIs) to configure the SNN’s connectivity, to compile the neuron-synapse model and to monitor SNN’s activity. Our contribution intends to provide a tool that allows to prototype SNNs faster than on CPU/GPU architectures but significantly cheaper than fabricating a customized neuromorphic chip. This could be potentially valuable to the computational neuroscience and neuromorphic engineering communities.

Multipumping Flexible DSP Blocks for Resource Reduction on Xilinx FPGAs

For complex datapaths, resource sharing can help reduce area consumption. Traditionally, resource sharing is applied when the same resource can be scheduled for different uses in different cycles, often resulting in a longer schedule. Multipumping is a method whereby a resource is clocked at a frequency that is a multiple of the surrounding circuit, thereby offering multiple executions per global clock cycle. This allows a single resource to be shared among multiple uses in the same cycle. This concept maps well to modern field-programmable gate arrays (FPGAs), where hard macro blocks are typically capable of running at higher frequencies than most designs implemented in the logic fabric. While this technique has been demonstrated for static resources, modern digital signal processing (DSP) blocks are flexible, supporting varied operations at runtime. In this paper, we demonstrate multipumping for resource sharing of the flexible DSP48E1 macros in Xilinx FPGAs. We exploit their dynamic programmability to enable resource sharing for the full set of supported DSP block operations, and compare this to multipumping only multipliers and DSP blocks with fixed configurations. The proposed approach saves on average 48% DSP blocks at a cost of 74% more LUTs, effectively saving 30% equivalent LUT area and is feasible for the majority of designs, in which clock frequency is typically below half the maximum supported by the DSP blocks.

An Error-Detection and Self-Repairing Method for Dynamically and Partially Reconfigurable Systems

Reconfigurable systems are gaining an increasing interest in the domain of safety-critical applications, for example in the space and avionic domains. In fact, the capability of reconfiguring the system during run-time execution and the high computational power of modern Field Programmable Gate Arrays (FPGAs) make these devices suitable for intensive data processing tasks. Moreover, such systems must also guarantee the abilities of self-awareness, self-diagnosis and self-repair in order to cope with errors due to the harsh conditions typically existing in some environments. In this paper we propose a self-repairing method for partially and dynamically reconfigurable systems applied at a fine-grain granularity level. Our method is able to detect correct and recover errors using the run-time capabilities offered by modern SRAM-based FPGAs. Fault injection campaigns have been executed on a dynamically reconfigurable system embedding a number of benchmark circuits. Experimental results demonstrate that our method achieves full detection of single and multiple errors, while significantly improving the system availability with respect to traditional error detection and correction methods.

LH-CAM: Logic-Based Higher Performance Binary CAM Architecture on FPGA

Binary content-addressable memory (BiCAM) is a popular high speed search engine in hardware, which provides output typically in one clock cycle. But speed of CAM comes at the cost of various disadvantages, such as high latency, low storage density, and low architectural scalability. In addition, field-programmable gate arrays (FPGAs), which are used in many applications because of its advantages, do not have hard IPs for CAM. Since FPGAs have embedded IPs for random-access memories (RAMs), several RAM-based CAM architectures on FPGAs are available in the literature. However, these architectures are especially targeted for ternary CAMs, not for BiCAMs; thus, the available RAM-based CAMs may not be fully beneficial for BiCAMs in terms of architectural design. Since modern FPGAs are enriched with logical resources, why not to configure them to design BiCAM on FPGA? This letter presents a logic-based high performance BiCAM architecture (LH-CAM) using Xilinx FPGA. The proposed CAM is composed of CAM words and associated comparators. A sample of LH-CAM of size ${64\times 36}$ is implemented on Xilinx Virtex-6 FPGA. Compared with the latest prior work, the proposed CAM is much simpler in architecture, storage efficient, reduces power consumption by 40.92%, and improves speed by 27.34%.

LUT based realization of fixed-point multipliers targeting state-of-art FPGAs

Look-up tables (LUT) form the basic logic elements in a large class of modern day field programmable gate arrays (FPGA). With FPGAs increasingly being used in low and medium volume productions, many vendors have improved the capacity and versatility of these devices. The enormous logic capacity inherent in state-of-art FPGAs has made it essential to develop automated computer aided design (CAD) support for logic synthesis using these platforms. Since design entry is the only manual phase in the FPGA CAD-flow, it essentially rules out any scope for technology-dependent optimization, which focusses on achieving optimal mapping of logical functionalities onto the target platforms. Evidently, majority of the work related to the implementation of different arithmetic circuits on FPGAs focuses only on the technology-independent optimizations, where the design process consists of modifying the architecture at the top level without giving any consideration to the mapping of the architecture onto the FPGA device. In this paper, we consider the technology-dependent optimization of the fixed-point bit-parallel multipliers on LUT based FPGAs. Our approach re-structures the initial Boolean network and transforms it into an optimized LUT netlist prior to the design entry phase. The design entry of the optimized netlist is then carried out using instantiation based coding styles. This ensures that the optimizations done prior to the design entry phase remain preserved throughout the synthesis process. We particularly focus on 6-input LUTs that are inherent basic logic elements in state-of-art FPGAs. Theoretical analysis and detailed experimentation using state-of-art Xilinx 7th generation FPGAs reveal a substantial speed-up in performance.

L1 track trigger for the CMS HL-LHC upgrade using AM chips and FPGAs

The increase of luminosity at the HL-LHC will require the introduction of tracker information in CMS’s Level-1 trigger system to maintain an acceptable trigger rate when selecting interesting events, despite the order of magnitude increase in minimum bias interactions. To meet the latency requirements, dedicated hardware has to be used. This paper presents the results of tests of a prototype system (pattern recognition ezzanine) as core of pattern recognition and track fitting for the CMS experiment, combining the power of both associative memory custom ASICs and modern Field Programmable Gate Array (FPGA) devices. The mezzanine uses the latest available associative memory devices (AM06) and the most modern Xilinx Ultrascale FPGAs. The results of the test for a complete tower comprising about 0.5 million patterns is presented, using as simulated input events traversing the upgraded CMS detector. The paper shows the performance of the pattern matching, track finding and track fitting, along with the latency and processing time needed. The pT resolution over pT of the muons measured using the reconstruction algorithm is at the order of 1% in the range 3-100 GeV/c.

Mapping for Maximum Performance on FPGA DSP Blocks

The digital signal processing (DSP) blocks on modern field programmable gate arrays (FPGAs) are highly capable and support a variety of different datapath configurations. Unfortunately, inference in synthesis tools can fail to result in circuits that reach maximum DSP block throughput. We have developed a tool that maps graphs of add/sub/mult nodes to DSP blocks on Xilinx FPGAs, ensuring maximum throughput. This is done by delaying scheduling until after the graph has been partitioned onto DSP blocks and scheduled based on their pipeline structure, resulting in a throughput optimized implementation. Our tool prepares equivalent implementations in a variety of other methods, including high-level synthesis (HLS) for comparison. We show that the proposed approach offers an improvement in frequency of 100% over standard pipelined code, and 23% over Vivado HLS synthesis implementation, while retaining code portability, at the cost of a modest increase in logic resource usage.