Abstract
The increase of luminosity at the HL-LHC will require the introduction of tracker information in CMS’s Level-1 trigger system to maintain an acceptable trigger rate when selecting interesting events, despite the order of magnitude increase in minimum bias interactions. To meet the latency requirements, dedicated hardware has to be used. This paper presents the results of tests of a prototype system (pattern recognition ezzanine) as core of pattern recognition and track fitting for the CMS experiment, combining the power of both associative memory custom ASICs and modern Field Programmable Gate Array (FPGA) devices. The mezzanine uses the latest available associative memory devices (AM06) and the most modern Xilinx Ultrascale FPGAs. The results of the test for a complete tower comprising about 0.5 million patterns is presented, using as simulated input events traversing the upgraded CMS detector. The paper shows the performance of the pattern matching, track finding and track fitting, along with the latency and processing time needed. The pT resolution over pT of the muons measured using the reconstruction algorithm is at the order of 1% in the range 3-100 GeV/c.
Highlights
For the High Luminosity (HL) upgrade of the Large Hadron Collider (LHC), scheduled for 2026, the number of proton-proton interactions per bunch crossing is predicted to reach 140 at the design instantaneous luminosity of 5×1034 cm−2s−1
A small prototype of the system has been built to prove that the associative memory (AM) plus Field Programmable Gate Array (FPGA) approach can satisfy CMS’ HL-LHC requirements
The full resolution data associated with these SuperStrip ID (SSID) are retrieved from the FPGA data-buffer, filtered and propagated to the Track Fitting module which fits the set of stubs with the same majority set in the AM chips
Summary
For the High Luminosity (HL) upgrade of the Large Hadron Collider (LHC), scheduled for 2026, the number of proton-proton interactions per bunch crossing (pile-up) is predicted to reach 140 at the design instantaneous luminosity of 5×1034 cm−2s−1. The first stage, called level-1 or L1 trigger, decides whether or not to save the information coming from the detector within few microseconds after the bunch crossing (event). This system is mainly implemented using hardware and firmware logic. For the HL phase of the LHC, the outer tracker of CMS will be redesigned, adopting a novel sensor technology to reduce the event information that is needed to be transferred from the detector to the data acquisition system. The pT module concept relies on the fact that the strips of both sensors are parallel to the beam axis in the barrel and nearly radial in the endcap, and uses the correlation of signals in closely-spaced sensors (a few millimeters) to make an angular measurement of the pair of hits. Our demonstration requires only a small extrapolation of the ASIC technology and cost of commercial devices, and depends on the assumption of a strong R&D program on the AM chip
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
