Threshold Voltage Model Research Articles

A Generalized Threshold Voltage Model of Tied and Untied Double-Gate Junctionless FETs for a Symmetric and Asymmetric Structure

A general potential model is proposed for all types of double-gate junctionless FETs (DGJL-FETs), i.e., the symmetric versus asymmetric DG structures and the tied versus untied DG structures. The potential model is obtained with a simple form through a 2-D Poisson’s equation based on the assumption that the vertical channel potential is approximated to a cubic function of the position in order to consider all types of DGJL-FETs. An analytical threshold voltage ( $V_{T})$ equation via the potential model is derived with the gate voltage when the sum of the depletion widths from the front-gate and the back-gate equals the body thickness. The analytic solution of $V_{T}$ shows good agreement with the simulation results down to a channel length $V_{T}$ is analyzed for various device parameters. The back-gate effect of the untied DG structure is also investigated.

A threshold voltage model of short-channel fully-depleted recessed-source/drain (Re-S/D) SOI MOSFETs with high-k dielectric**The author, Pramod Kumar Tiwari, was supported by the Science and Engineering Research Board (SERB), Department of Science and Technology, Ministry of Human Resource and Development, Government of India under Young Scientist Research (Grant No. SB/FTP/ETA-415/2012).

In this paper, a surface potential based threshold voltage model of fully-depleted (FD) recessed-source/drain (Re-S/D) silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistor (MOSFET) is presented while considering the effects of high-k gate-dielectric material induced fringing-field. The two-dimensional (2D) Poisson’s equation is solved in a channel region in order to obtain the surface potential under the assumption of the parabolic potential profile in the transverse direction of the channel with appropriate boundary conditions. The accuracy of the model is verified by comparing the model’s results with the 2D simulation results from ATLAS over a wide range of channel lengths and other parameters, including the dielectric constant of gate-dielectric material.

Localized Charge-Dependent Threshold Voltage Analysis of Gate-Material-Engineered Junctionless Nanowire Transistor

In this paper, the threshold voltage analysis of junctionless nanowire transistor (JNT) due to radiation/ process/stress/hot-carrier damage-induced localized/fixed charges at elevated temperatures is discussed. A temperature-dependent threshold voltage model for JNT with localized charges has been developed including the source/drain depleted regions. The impact of position, density, and polarity of localized charges on channel potential, bandgap energy, and threshold voltage is studied. Four different localized charge density profiles have been used to evaluate the performance degradation. The results demonstrate that localized charges significantly change the device threshold voltage and temperature sensitivity and show less detrimental effect at elevated temperatures.

A new analytical threshold voltage model of cylindrical gate tunnel FET (CG-TFET)

The cylindrical gate tunnel FET (CG-TFET) is one of the potential candidates for future nano-technology, as it exhibit greater scaling capability and low subthreshold swing (SS) as compared to conventional MOSFET. In this paper, a new analytical approach is proposed to extract the gate dependent threshold voltage for CG-TFET. The potential distribution and electric field distribution in the cylindrical channel has been obtained using the 2-D Poisson’s equation which in turn computes the shortest tunneling distance and tunneling current. The threshold voltage is extracted using peak transconductance change method based on the saturation of tunneling barrier width. The impact of scaling of effective oxide thickness, cylindrical pillar diameter and gate length on the threshold voltage has been investigated. The consistency of the proposed model is validated with the TCAD simulated results. The present model can be a handful for the study of switching behavior of TFET.

A Two-Dimensional Gate Threshold Voltage Model for a Heterojunction SOI-Tunnel FET With Oxide/Source Overlap

A two-dimensional (2D) analytical gate threshold voltage model for a heterojunction silicon-on-insulator tunnel field-effect transistor structure with gate oxide overlap is developed. The infinite series method, with suitable boundary conditions, is used to solve the 2D Poisson’s equation for surface potential. The surface potential is used to develop the expression for the proposed analytical threshold voltage in closed form. Developed threshold voltage is verified for different gate length, drain voltage, oxide thickness, and gate dielectric materials against Synopsys Technology Computer-Aided Design numerical simulation results and found to predict the simulated results accurately.

Analytical modeling of threshold voltage for Cylindrical Gate All Around (CGAA) MOSFET using center potential

Abstract In this paper, an analytical threshold voltage model is proposed for a cylindrical gate-all-around (CGAA) MOSFET by solving the 2-D Poisson’s equation in the cylindrical coordinate system. A comparison is made for both the center and the surface potential model of CGAA MOSFET. This paper claims that the calculation of threshold voltage using center potential is more accurate rather than the calculation from surface potential. The effects of the device parameters like the drain bias ( V DS ) , oxide thickness ( t ox ) , channel thickness (r), etc., on the threshold voltage are also studied in this paper. The model is verified with 3D numerical device simulator Sentaurus from Synopsys Inc.

Potential‐based threshold voltage and subthreshold swing models for junctionless double‐gate metal‐oxide‐semiconductor field‐effect transistor with dual‐material gate

SummaryOn the basis of quasi‐two‐dimensional solution of Poisson's equation, an analytical threshold voltage model for junctionless dual‐material double‐gate (JLDMDG) metal‐oxide‐semiconductor field‐effect transistor (MOSFET) is developed for the first time. The advantages of JLDMDG MOSFET are proved by comparing the central electrostatic potential and electric field distribution with those of junctionless single‐material double‐gate (JLSMDG) MOSFET. The proposed model explicitly shows how the device parameters (such as the silicon thickness, oxide thickness, and doping concentration) affect the threshold voltage. In addition, the variations of threshold voltage roll‐off, drain‐induced barrier lowering (DIBL), and subthreshold swing with the channel length are investigated. It is proved that the device performance for JLDMDG MOSFET can be changed flexibly by adjusting the length ratios of control gate and screen gate. The model is verified by comparing its calculated results with those obtained from three‐dimensional numerical device simulator ISE. Copyright © 2015 John Wiley & Sons, Ltd.

Analytical Modeling and Experimental Validation of Threshold Voltage in BSIM6 MOSFET Model

In this paper, an analytical model of threshold voltage for bulk MOSFET is developed. The model is derived from the physical charge-based core of BSIM6 MOSFET model, taking into account short channel effects, and is intended to be used in commercial SPICE simulators for operating point information. The model is validated with measurement data from IBM 90-nm technology node using various popular threshold voltage extraction techniques, and good agreement is obtained.

A two-dimensional analytical model for short channel junctionless double-gate MOSFETs

A physics-based analytical model of electrostatic potential for short-channel junctionless double-gate MOSFETs (JLDGMTs) operated in the subthreshold regime is proposed, in which the full two-dimensional (2-D) Poisson’s equation is solved in channel region by a method of series expansion similar to Green’s function. The expression of the proposed electrostatic potential is completely rigorous and explicit. Based on this expression, analytical models of threshold voltage, subthreshold swing, and subthreshold drain current for JLDGMTs were derived. Subthreshold behavior was studied in detail by changing different device parameters and bias conditions, including doping concentration, channel thickness, gate length, gate oxide thickness, drain voltage, and gate voltage. Results predicted by all the analytical models agree well with numerical solutions from the 2-D simulator. These analytical models can be used to investigate the operating mechanisms of nanoscale JLDGMTs and to optimize their device performance.

A New Quasi-3-D Compact Threshold Voltage Model for Pi-Gate (ΠG) MOSFETs With the Interface Trapped Charges

With the effects of equivalent oxide charges on the flat-band voltage, a new quasi-three-dimensional (quasi-3-D) compact threshold voltage model is presented for the pi-gate (ΠG) MOSFETs with the interface trapped charges based on the quasi-3-D scaling equation that accounts for equivalent number of gates and virtual back gate effects induced by the normalized gate extension depth in the buried oxide. The model reveals that a thin gate oxide can effectively reduce the threshold voltage degradation caused by the trapped charges. Opposite to the thin gate oxide, a thick silicon is required to alleviate the threshold voltage shift resulted from the negative trapped charges. For the short-channel behavior, the device with negative/positive trapped charges can decrease/increase the threshold voltage roll-off caused by the short-channel effects. Due to its computational efficiency and simple formula, the model can be easily used to explore the threshold behavior for the charges trapping ΠG MOSFETs.

A Stabilization Technique for Single-Ended and Differential Harmonic Oscillators

A stabilization technique is presented for harmonic oscillators which can reduce deviation of radio-frequency parameters against process variation. The stabilizing gate circuit (SGC) is designed to improve fidelity of oscillation amplitude, phase noise, and period jitter without a significant increase in power requirement. Process-related phenomena such as device aging, feature size uncertainty, and supply ripples are covered through modeling of threshold voltage, device dimension, and power rail variation. Single-ended and differential circuits of inductor-capacitor (LC)- tuned Hartley harmonic oscillators are simulated with 90-nm device parameters to verify the SGC's effectiveness for diverse front ends. The technique is able to reduce variability of phase noise and period jitter by up to 34 dBc/Hz and 76 fs over a wide range of offset frequencies (10$$^3$$3---10$$^6$$6 Hz). It also improves stability of oscillation amplitude by up to 29 % and performs better than other reported process compensation mechanisms.

A Novel Quasi-3D Interface-Trapped-Charge-Degraded Threshold Voltage Model for Omega-Gate <inline-formula> <tex-math notation="TeX">$(\Omega{G})$</tex-math></inline-formula> MOSFETs

With the effects of equivalent oxide charges on the flat-band voltage, we report a novel quasi-3D interface-trapped-charge-degraded threshold voltage model for omega-gate (ΩG) MOSFETs based on the quasi-3D scaling equation, including the equivalent number of gates. It is found that a thin gate oxide is required to reduce threshold voltage degradation by the trapped charges. For the positive/negative trapped charges, the damaged device with a thick/thin silicon film suffers from small/large threshold voltage degradation. In addition, a large/ small oxide-to-gate underlap coverage factor can be adjusted to improve the threshold voltage degradation by the positive/negative trapped charges. For the short-channel behavior, a damaged device with the negative trapped charges is better than the one with the positive trapped charges. The model can be used to explore the hot-carrier-induced threshold voltage degradation of the ΩG MOSFET for its memory cell application.

Influences of fringing capacitance on threshold voltage and subthreshold swing of a GeOI metal-oxide-semiconductor field-effect transistor**Project supported by the National Natural Science Foundation of China (Grant No. 61274112).

Models of threshold voltage and subthreshold swing, including the fringing-capacitance effects between the gate electrode and the surface of the source/drain region, are proposed. The validity of the proposed models is confirmed by the good agreement between the simulated results and the experimental data. Based on the models, some factors impacting the threshold voltage and subthreshold swing of a GeOI metal-oxide-semiconductor field-effect transistor (MOSFET) are discussed in detail and it is found that there is an optimum thickness of gate oxide for definite dielectric constant of gate oxide to obtain the minimum subthreshold swing. As a result, it is shown that the fringing-capacitance effect of a short-channel GeOI MOSFET cannot be ignored in calculating the threshold voltage and subthreshold swing.

A compact quasi 3D threshold voltage modeling and performance analysis of a novel linearly graded binary metal alloy quadruple gate MOSFET for subdued short channel effects

In the present era of low power devices, to keep pace with the aggressive scaling demands, the concept of surrounding gate MOS geometry is gradually being popular among the researchers for enhancing the performance of nanoscale MOSFETs due to the inherent benefit of the gate-all-around geometry compared to the conventional planar structures. In this research endeavour, we have, for the first time, incorporated the novel theory of work function engineering of a binary metal alloy gate with continuous horizontal variation of mole fraction in a fully depleted quadruple gate MOSFET, thereby proposing a new structure namely Work Function Engineered Gate Quadruple Gate MOSFET (WFEG QG MOSFET). A detailed analytical modeling of this novel WFEG QG MOS structure has been formulated to present a quasi 3D threshold voltage model based on 3D scaling equation instead of the tedious solution of 3D Poisson’s equation. The device short channel effects have been included by calculating the natural length of the proposed QG device using the effective number of gate (ENG) concept. An overall comparative performance analysis of the WFEG QG MOS and normal QG MOSFET has been done to establish the superiority of the proposed WFEG structure over its QG equivalent in terms of reduced Short Channel Effects (SCEs), Drain Induced Barrier Lowering (DIBL) and Threshold Voltage Roll Off (TVRO). The results of our analytical modeling are found to be in good agreement with the simulation results, thereby establishing the accuracy of our modeling.

Analytical subthreshold modeling of dual material gate engineered nano-scale junctionless surrounding gate MOSFET considering ECPE

In this paper, we propose a new two-dimensional (2-D) analytical model of dual material junctionless surrounding gate MOSFET (DMJLSRG MOSFET). The expressions of potential and Electric Field of the gate engineered MOSFET structure have been obtained by solving the 2-D Poisson’s equation in subthreshold regime using a parabolic potential approximation considering effective conduction path effect (ECPE). The developed potential model accurately predicts the perceivable step function in the potential profile, responsible for effective screening of the drain potential variation in order to reduce DIBL and threshold voltage roll-off. In this work, effectiveness of dual material gate engineered (DM) design for junctionless MOSFET was scrutinized by comparing the results with a single material gate junctionless surrounding gate MOSFET (SMJLSRG MOSFET) of same dimension. From the developed potential model, a simple and accurate analytical expression of threshold voltage is also derived. Results reveal that DMJLSRG devices offer superior performance as compared to SMJLSRG devices. An improvement of hot-carrier effects (HCEs) and a reduction of short-channel effects (SCEs) have been demonstrated for gate-engineered DMJLDG device over the corresponding conventional (SMJLDG) device. The proposed model can be used as a basic design guideline for gate-engineered junctionless surrounding gate MOSFETs.

Modeling and comparative analysis of DC characteristics of AlGaN/GaN HEMT and MOSHEMT devices

AbstractIn this paper, a charge control model is developed for AlGaN/GaN High Electron Mobility Transistor (HEMT) and Metal Oxide Semiconductor High Electron Mobility Transistor (MOSHEMT) by considering the triangular potential well in the two‐dimensional electron gas (2DEG) and simulated with matlab. The obtained results from the developed model are compared with the experimental data for drain current, transconductance, gate capacitance and threshold voltage of both devices. The physics‐based models for 2DEG charge density, threshold voltage and gate capacitance have been developed. By using these developed models, the drain current for both linear and saturation modes is derived. The predicted threshold voltage with the variation of barrier thickness has been plotted. A positive threshold voltage can be obtained by decreasing the barrier thickness that builds up the foundation for enhancement mode MOSHEMTs. The predicted C‐V, Id‐Vgs, Id‐Vds and transconductance characteristics show an excellent agreement with the experimental results from the literature and hence validate the developed model. The results clearly establish the potential of using AlGaN/GaN MOSHEMT approach for high power microwave and switching applications. Copyright © 2015 John Wiley & Sons, Ltd.

An analytical model of triple‐material double‐gate metal–oxide–semiconductor field‐effect transistor to suppress short‐channel effects

SummaryThis paper presents an analytical subthreshold model for surface potential and threshold voltage of a triple‐material double‐gate (DG) metal–oxide–semiconductor field‐effect transistor. The model is developed by using a rectangular Gaussian box in the channel depletion region with the required boundary conditions at the source and drain end. The model is used to study the effect of triple‐material gate structure on the electrical performance of the device in terms of changes in potential and electric field. The device immunity against short‐channel effects is evaluated by comparing the relative performance parameters such as drain‐induced barrier lowering, threshold voltage roll‐off, and subthreshold swing with its counterparts in the single‐material DG and double‐material DG metal–oxide–semiconductor field‐effect transistors. The developed surface potential model not only provides device physics insight but is also computationally efficient because of its simple compact form that can be utilized to study and characterize the gate‐engineered devices. Furthermore, the effects of quantum confinement are analyzed with the development of a quantum‐mechanical correction term for threshold voltage. The results obtained from the model are in close agreement with the data extracted from numerical Technology Computer Aided Design device simulation. Copyright © 2015 John Wiley & Sons, Ltd.

A Model of channel current for uniaxially strained Si NMOSFET

The channel current model is used to analyse the behavior of uniaxially strained Si NMOSFET device and circuit. With the development of mobility and threshold voltage model, starting from the basic drift-diffusion equation, the channel current model for an uniaxially strained Si NMOSFET device is developed under different bias conditions. Especially, the stress intensity is explicitly included in the mobility and threshold voltage model, and this makes the model convenient to directly reflect the relationship between the device channel current and the stress intensity. Moreover, in terms of the subthreshold current model, the charge of weak inversion rather than the normal effective channel thickness approximation is involved. In this way, the model accuracy can be improved. Furthermore, this model is implemented by using verilogA language and is applied to the strained Si circuit's SPICE simulation, the model parameters extraction tool ParamPlus++ is developed at the same time. As a result, the simulation of uniaxial-strained Si NMOSFET device and circuit can be achieved; the simulation data fits the experimental results or TCAD simulation results very well, and this proves the accuracy of the model. Meanwhile the simulation results of the threshold voltage and subthreshold current with respect to stress intensity are obtained and analyzed. The results show that with increasing stress intensity the subthreshold current is increased while the threshold voltage is decreased.

Explicit Analytical Current-Voltage Model for Double-Gate Junctionless Transistors

An explicit analytical model for long-channel double-gate junctionless transistors is presented in each operation mode: 1) full depletion; 2) partial depletion; and 3) accumulation. The proposed model calculates potentials, electric fields, mobile charges, and drain current without any implicit function or special functions. The results obtained with the proposed model agree well with the results obtained with a 2-D technology computer-aided design simulation in all modes of operation and for various device structures. Furthermore, a physical insight is provided into reducing variability using the threshold voltage model.

이중게이트 MOSFET의 대칭 및 비대칭 산화막 구조에 대한 문턱전압 분석

본 연구에서는 대칭 및 비대칭 산화막 구조를 가진 이중게이트(double gate; DG) MOSFET의 문턱전압 변화에 대하여 분석하였다. 상하단 동일한 산화막 두께을 갖는 대칭 DGMOSFET와 달리 비대칭 DGMOSFET는 상하단 게이트 산화막 두께를 다르게 제작할 수 있다. 그러므로 비대칭 DGMOSFET에서 상단과 하단게이트 산화막 두께의 크기 변화에 따라 대칭 DGMOSFET와 문턱전압을 비교하여 상하단 게이트 산화막 두께의 최적값에 대하여 고찰하고자 한다. 문턱전압을 구하기 위하여 포아송방정식에서 해석학적 전위분포모델을 유도하였으며 도핑분포함수는 가우스분포함수를 사용하였다. 문턱전압 모델을 이용하여 하단게이트 전압, 채널길이 및 채널두께 등에 따라 상하단게이트 산화막 두께가 문턱전압에 미치는 영향을 관찰하였다. 결과적으로 문턱전압은 상하단 게이트 산화막 두께에 따라 크게 변화하였으며 변화하는 경향은 하단게이트 전압, 채널길이 그리고 채널두께에 따라 매우 상이하게 나타나고 있다는 것을 알 수 있었다. This paper has analyzed the change of threshold voltage for oxide structure of symmetric and asymmetric double gate(DG) MOSFET. The asymmetric DGMOSFET can be fabricated with different top and bottom gate oxide thickness, while the symmetric DGMOSFET has the same top and bottom gate oxide thickness. Therefore optimum threshold voltage is considered for top and bottom gate oxide thickness of asymmetric DGMOSFET, compared with the threshold voltage of symmetric DGMOSFET. To obtain the threshold voltage, the analytical potential distribution is derived from Possion's equation, and Gaussian distribution function is used as doping profile. We investigate for bottom gate voltage, channel length and thickness, and doping concentration how top and bottom gate oxide thickness influences on threshold voltage using this threshold voltage model. As a result, threshold voltage is greatly changed for oxide thickness, and we know the changing trend greatly differs with bottom gate voltage, channel length and thickness, and doping concentration.