MOSFET Model Research Articles

Characterization and compact modeling of short channel MOSFETs at cryogenic temperatures

This paper presents an overall characterization, physics-based device analysis, and compact modeling of a commercial 110nm bulk CMOS technology. I−V measurements and DC parameters extraction are performed on low threshold voltage (low VTH, LVT) and regular VTH (RVT) devices with various geometry dimensions from 300 K to 6 K. Different levels of improvement of subthreshold swing (SS), OFF-state current (IOFF), and mobility indicates the potential to optimize the performance of circuits at cryogenic temperatures. However, the temperature characteristics of the mobility and series resistance show a great dependence on the channel length of the devices, which complicates the calculation of the ON-state current at cryogenic temperatures. Moreover, VTH roll-off caused by short channel effect (SCE) get worse, which can be attributed to the increased bulk Fermi potential (ϕf). These channel-length-related effects add extra challenges to the design of cryogenic circuits. An optimized compact model based on BSIM4 is proposed to capture the device characteristics at 6 K, which can produce accurate simulation results only through parameter configuration rather than model equation modification and has been applied to the design of cryogenic CMOS circuits.

Simulation of Transport Moiré Pattern in Van Der Waals Heterostructures

Vertically stacking two-dimensional (2D) materials with different lattice constants will generate a Moiré pattern with a nanometer-scale periodicity. Here, we theoretically demonstrate the transport Moiré patterns on the surfaces of stacked 2D materials. In the MOSFET model, the electrons accumulate at high Moiré potential regions, while they dissipate at the others, along the gate voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{g}{)}$ </tex-math></inline-formula> until high current levels. As an application of the inhomogeneous transport, we show that the Moiré pattern can be used to restrain the effect of edge defects in one-dimensional ribbons by modulating the potentials of the edge and middle regions. Simulation results show that the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{g}$ </tex-math></inline-formula> deviations can be substantially reduced when different kinds of edge defects are randomly added, such as vacancies and foreign dopants, suggesting the suitability of Moiré pattern in defect engineering.

An Accurate Analytical Model of SiC MOSFETs for Switching Speed and Switching Loss Calculation in High-Voltage Pulsed Power Supplies

Nanosecond output pulse and high efficiency are achieved in high-voltage pulsed power supplies (HVPPSs) by applying silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors ( <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s), whose switching speed and switching loss are two vital characteristic parameters. However, the existing research on switching characteristics of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s is mainly based on the double pulse test circuits with inductive loads, which is not suitable for assessing the devices in HVPPSs with resistive loads. Besides, some simplified analytical methods in HVPPSs lead to poor precision. To accurately predict the switching behavior of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s in HVPPSs for guiding the design of gate driving circuits and power loops, this article proposes an accurate analytical model considering parasitic inductances, nonlinear parasitic capacitances, transfer characteristic, and output characteristics of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s. High-precision fitting of transfer characteristic is realized by using the Gaussian function. Besides, the dynamic parasitic gate-drain capacitance is measured by experiment, and three-dimensional curve fitting is performed on the output characteristics to exactly represent <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -resistance. Furthermore, switching speed and switching loss can be directly calculated according to the solved state variables. Finally, the analytical model is verified by experiment, and the effects of gate driving circuits and power loops on switching characteristics are researched in detail.

Simulation of a ring oscillator operation during γ-ray irradiation using the TID response model of MOSFETs and its experimental verification

The response of N-type MOSFET characteristics to TID (Total Ionizing Dose) effects caused by γ-ray irradiation was modeled as a sum of two exponential functions which expresses the charge accumulation of the oxide traps and the interface traps respectively. This model was applied to the circuit simulation of a ring oscillator operation. It was shown that the simulation result reproduces the variation in the measured oscillation frequency experimentally. The simulation also showed that there is an optimum size ratio between N-type MOSFET and P-type MOSFET which can minimize the variation in oscillation frequency due to TID effects. These obtained results verified that the proposed method can be applied to the prediction of response in a dynamic operation circuit to TID effects.

Research on the Switching Characteristics Based on the SiC MOSFET Model

With the continuous development of power electronics technology, the third-generation semiconductor materials represented by SiC and GaN have significant advantages in the band gap width, breakdown electric field, thermal conductivity, electron saturation rate and other key parameters, which meet the needs of modern industry for high power, high voltage and high frequency. When the SiC MOSFET plays its high frequency advantage, with the increase of switching frequency, the voltage change rate and current change rate of the device will be larger in the process of turning on and off. This paper mainly analyzes the characteristics of SiC MOSFET devices, and modifies the model based on the model provided by the manufacturer. By establishing static and dynamic test circuits, the static characteristic curves of the model were observed, and the drain voltage and current waveforms of the original model and the optimized model were compared during the switching process. The results show that the switching time of the optimized model is improved, and the oscillation waveform is greatly improved. Then, the accuracy of the optimized model is verified by the double-pulse circuit, and the drain source voltage and the drain source current are studied and observed under different temperature and drive resistance conditions. This paper provides data support for improving the switching characteristics of SiC MOSFET in practical applications.

Parameter extraction and selection for a scalable N-type SiC MOSFETs model and characteristic verification along with conventional dc-dc buck converter integration.

Most silicon carbide (SiC) MOSFET models are application-specific. These are already defined by the manufacturers and their parameters are mostly partially accessible due to restrictions. The desired characteristic of any SiC model becomes highly important if an individual wants to visualize the impact of changing intrinsic parameters as well. Also, it requires a model prior knowledge to vary these parameters accordingly. This paper proposes the parameter extraction and its selection for Silicon Carbide (SiC) power N-MOSFET model in a unique way. The extracted parameters are verified through practical implementation with a small-scale high power DC-DC 5 to 2.5 output voltage buck converter using both hardware and software emphasis. The parameters extracted using the proposed method are also tested to verify the static and dynamic characteristics of SiC MOSFET. These parameters include intrinsic, junction and overlapping capacitance. The parameters thus extracted for the SiC MOSFET are analyzed by device performance. This includes input, output transfer characteristics and transient delays under different temperature conditions and loading capabilities. The simulation and experimental results show that the parameters are highly accurate. With its development, researchers will be able to simulate and test any change in intrinsic parameters along with circuit emphasis.

Accelerated degradation modeling of power MOSFET under multiple stresses

Power MOSFET is one of the most critical components in power electronic converters. However, it often performs a lower reliability index under multiple stresses. Conventional single-stress accelerated degradation test (ADT) and corresponding statistical inference are unable to evaluate its reliability accurately. In this article, a new accelerated degradation model is designed by combining multi-stress accelerated model and the generalized Wiener process model. This comprehensive model not only establishes the relationship between drift coefficient and multiple stresses but also take the nonlinearity and uncertainties existing in degradation process into consideration. Subsequently, an ADT with temperature, electrical and vibration stresses for power MOSFET is carried out to obtain the degradation data under different stress levels, which is employed for unknown parameter estimation. Comparative analysis demonstrates that the proposed model can provide a more accurate and reasonable reliability assessment result. Keywords-accelerated

Knowledge-based neural network SPICE modeling for MOSFETs and its application on 2D material field-effect transistors

Knowledge-based neural network SPICE modeling for MOSFETs and its application on 2D material field-effect transistors

A Datasheet-Driven Nonsegmented Empirical SPICE Model of SiC MOSFET With Improved Accuracy and Convergence Capability

This article presents a datasheet-driven empirical model of silicon carbide (SiC) MOSFET, in which both the static <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> and dynamic <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> characteristics are accurately captured by using nonsegmented empirical equations. Compared with the existing models, this model features on describing the first quadrant conduction <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> characteristics through nonsegmented empirical equations while considering the intrinsic physical mechanisms, which is beneficial for improving the convergence capability. Moreover, the nonlinear Miller capacitance <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}_{gd}$ </tex-math></inline-formula> is accurately captured considering the shielding effect caused by the adjacent p-wells. Apart from the abovementioned added features, a parameter extraction procedure is also proposed, in which all the parameter values could be directly extracted from the data provided in the commercial datasheet. The accuracy of the proposed model is verified through the comparisons between the modeling results and experimental data from the datasheet. Furthermore, the convergence capability of the proposed model is verified by simulating a seven-level cascaded H-bridge (CHB) inverter, in which 12 devices are included. The experimental double pulse test is finally carried out to verify the feasibility of the proposed model in simulating the dynamic transients.

Corrections to “Design-Oriented All-Regime All-Region 7-Parameter Short-Channel MOSFET Model Based on Inversion Charge”

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Improved SiC MOSFET Model Considering Channel Dynamics of Transfer Characteristics

An improved SiC MOSFET model is proposed in this article, which predicts the dynamics accurately in the wide operation range of the SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> . The temperature-sensitive effect (TSE), the short channel effect (SCE), and the interface state effect are comprehensively taken into consideration in the modeling of the transfer characteristics. A dynamic test platform of transfer characteristics is designed to extract data better than the datasheet. The turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> and turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> processes of the SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> are decoupled, and the nonlinear interterminal capacitances are also modeled thoroughly. To verify the convergence and accuracy of the proposed model, a 400 V/30 A double pulse test is fulfilled, and the complex converters are also simulated with the proposed model. The results show that the proposed model has good convergence and accuracy in predicting the switching trajectory of the SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> , which would be favorable for observing the dynamics in the high-speed switching processes of the SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> .

Design and Optimization of Ultradeep Submicron CMOS Inverter Using a Unified All Regional MOSFET Model

Complementary Metal Oxide Semiconductor (CMOS) has always remained the dominant integrated circuit technology specifically for designing digital circuits. This paper examines the modelling (utilizing $\alpha$-power based MOSFET model), simulation (utilizing HSPICE simulation) and optimization (utilizing Particle Swarm Optimization (PSO) and Artificial Bee Colony (ABC) techniques) of ultradeep submicron CMOS based digital inverter, performs insightful analysis and extracts formulas for the optimal transistor sizing. Additionally, the study serves as an implementation forum for the thermal analysis of transient characteristics of CMOS inverters at the ultradeep submicron technology node (at 300K and 400K). The results lie within the acceptable range of 1-10\%.

Electro-Thermal simulation study of MOSFET modeling in Silicon and Silicon carbide

In this paper, a 2D electro-thermal coupling model of a MOSFET power device is presented using COMSOL Multiphysics software. The main objective of the model is to investigate and analyze the effect of temperature change on the electrical characteristics of a lateral MOSFET, visualize the heat distribution throughout the device, and calculate the peak temperature reached under extreme conditions. Thus, a comparison study is performed between Si and 6H-SiC based devices to highlight the effect of device material on its performance. The temperature distribution and the maximum temperature reached in both Si and 6H-SiC MOSFETs evaluate the reliability of the power component. The obtained results reveal lower drain currents and hot spot temperature values &nbsp;lower in 6H-SiC MOSFET.

A physics-based compact model of shield gate trench MOSFET

This paper develops a physics-based compact model of shield gate trench (SGT) MOSFET, including a drift region current, an analytical intrinsic drain potential and a charge on the capacitance between shield gate (SG) and the drift region. In order to describe the depletion in the drift region caused by SG, a drift region current model including velocity saturation is proposed to obtain I–V characteristics. An analytical model of the intrinsic drain potential is used for the charge model to correct CGD in the off-state, and a charge on the capacitance between SG and the drift region is added to the model to obtain precise CDS. The proposed charge model can capture the behaviors of the capacitance saturation caused by SG. The experimental data of 45V SGT MOSFET on I–V, C–V, QG and transient characteristics demonstrates the accuracy of the presented model.

Performance Evaluation of Bidirectional SEPIC-ZETA DC-DC Converter with Different Ambient Temperature

Bidirectional DC-DC converters allow power to be transferred in any direction between two electrical sources. These converters are increasingly employed in a variety of applications, including battery chargers and dischargers, energy storage devices, electrical vehicle motor drives, aircraft power systems, telecom power supplies, and others, due to their ability to reverse the direction of power flow. One of these basic types of bidirectional DC-DC converters is the SEPIC-ZETA converter. In this paper, the structure of this converter has been studied when MOSFET power switches are employed. Also, an electrical thermal analysis, which is based on the ambient temperature (between 25 °C and 40 °C), has been employed by using two MOSFET models (UJ3C065080K3S and SCT50N120). The study shows the effects of utilizing different MOSFET models on power losses and thermal analysis. According to the simulation results, the junction temperature of the MOSFET was 151.38 °C in the forwarding mode and for the first model (UJ3C065080K3S) at T = 40 °C, while the MOSFET junction temperature was 158.5 °C in the backward mode. In the second model (SCT50N120) and at the same T = 40°C, the MOSFET junction temperature exceeds 130.6°C in the forwarding mode. When the converter was operating in backward mode, its junction temperature was 128.7 °C. The bidirectional SEPIC-ZETA converter performs better in the second model of the MOSFET (SCT50N120).

Hierarchical Mixture-of-Experts approach for neural compact modeling of MOSFETs

With scaling, physics-based analytical MOSFET compact models are becoming more complex. Parameter extraction based on measured or simulated data consumes a significant time in the compact model generation process. To tackle this problem, ANN-based approaches have shown promising performance improvements in terms of accuracy and speed. However, most previous studies used a multilayer perceptron (MLP) architecture which commonly requires a large number of parameters and train data to guarantee accuracy. In this article, we present a Mixture-of-Experts approach to neural compact modeling. It is 78.43% more parameter-efficient and achieves higher accuracy using fewer data when compared to a conventional neural compact modeling approach. It also uses 43.8% less time to train, thus, demonstrating its computational efficiency.

Active Junction Temperature Control for SiC MOSFETs Based on a Resistor-Less Gate Driver

Junction temperature fluctuation is the main cause of failure of power devices including silicon carbide (SiC) MOSFETs, and active junction temperature control is an effective way to improve their reliability. Most existing methods of active junction temperature control rarely consider the system efficiency and the complexity of hardware implementation, which limits their applications. This article proposes an active junction temperature control method for SiC MOSFETs based on a resistor-less gate driver, which consists of two auxiliary MOSFETs with adjustable gate–source voltages. Hence, the switching loss of the SiC MOSFET can be continuously and accurately adjusted to mitigate the efficiency suffer with the junction temperature control. The power loss model of SiC MOSFETs with the proposed gate driver was established. The design principle of the junction temperature controller is introduced. The experimental results show that the junction temperature fluctuation is reduced by 24.1%, and that the lifetime of the SiC MOSFET is prolonged by 3.92 times via using the proposed junction temperature control method. The energy loss of the prototypical inverter is decreased by 4.15% over the whole testing period. The experiment was conducted with SiC MOSFETs, and the proposed method is also suitable for other Si-based semiconductor devices.

AN ANALYTICAL MODEL OF SUBSTRATE CURRENT IN A SHORT CHANNEL MOSFET

The drain characteristics of a short channel MOSFET operating in the avalanche multiplication regime depends strongly on the flow of substrate current . In this work, the detailed physics and the corresponding mathematical analysis of the substrate current model of a short channel MOSFET in its avalanche multiplication regime has been presented, which can be used to find the different characteristics of the short channel MOSFET for a wide range of device parameters. It is shown that by using a multiplication model, the substrate current can be obtained for a particular drain source voltage . The model system shows excellent results, which were confirmed by the computer-aided simulation program (MATLAB).

An Improved Equivalent Circuit Model of SiC MOSFET and Its Switching Behavior Predicting Method

Wide-bandgap (WBG) power devices have better dynamic characteristics and higher working temperatures compared to traditional Si devices and are more suitable for high-frequency and high-voltage applications because of fast turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> and turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> speeds. The main obstacle for the use of WBG devices is the high-frequency oscillation (HF-Osc) in voltage and current during the switching process. In this article, a new method of predicting the SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> switching behavior (including HF-Osc and slow switching) is proposed. First, the models of nonlinear capacitances are improved and parasitic elements are taken into account for improving the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RLC</i> equivalent circuit of the <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> switching transient. On this basis, the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> equivalent frequency is obtained. Then, a new method is proposed to obtain the SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> instantaneous frequency. The comparison between them in the time domain makes it possible to analyze the SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> switching behavior. The prediction method is verified using a CREE SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> via a double pulse test. Experimental and simulation results show that the prediction method is effective in describing the HF-Osc characteristics. The proposed method can be used to effectively improve the <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> HF-Osc, which provides guidance for the application of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s.

A Compact Model of Ferroelectric Field-Effect Transistor

In this letter, we present a compact model of ferroelectric field-effect-transistor (FEFET). The model consists of a ferroelectric (FE) capacitor model and a Berkeley Short-channel IGFET Model (BSIM), a standard SPICE MOSFET model. The FE model, similar to the nucleation-limited-switching model, is based on the statistical multidomain dynamics of FE materials. The charge equality between FE and MOSFET is satisfied through the SPICE simulator. The model reproduces the steep switching in the reverse bias region observed in experimental FEFETs and the current drop at both major loop and minor loop switching. A versatile inverted-memory-window (IMW) model can model the IMW behavior of FEFET that may be caused by charge trapping. We demonstrate that the reported model can accurately fit the published data of Fin-FEFET and FDSOI-FEFET under different bias conditions.