Model Of Through Silicon Via Research Articles

Enhancement of liner materials based on nanomaterials to promote sustainability in noise intercourse

Daily usage of devices has had a major influence on lives and existence, which would be unimaginable without them. Due to this, recent gadget dependability concerns need particular attention. PCs, hand mobile phones, and other computerized household gadgets need integrated circuits (ICs). Individual components must work together to accomplish their tasks and make the circuit operate. Hot carrier effect, oxide breakdown, and other system-level problems result from accommodating several devices in a planar IC. Vertical linking active components in one IC to another IC is a common method of three-dimensional IC integration (3D-IC). The main issue with 3D-IC adoption is electrical interference to neighboring through silicon via (TSV) and active transistors, which substantially reduces system performance. The electrical TSV (ETSV) model, which employs solely electrical signal carrying TSV, and the thermal TSV (TTSV) model, which incorporates thermal TSV during simulation, are used in this research to reduce electrical interference. The electrical signal transporting TSV to the substrate and other TSV was investigated for interference. With other models, this study also shows higher frequency regimes up to 1 THz. We found that the suggested methodology improves 3D-IC development by more than 30% by reducing electrical interference from signal-carrying TSV to other TSV.

Noise coupling reduction using temperature enhanced device for future integrated circuit integration applications

<p>Information technology-to-internet of things may have succeeded because of fast silicon chip capability expansion. Moore's law, which reduces device size, boosted integrated circuit (IC) performance. Delay rises with highdensity connection parasitic capacitance. Interconnect delays have surpassed transistor delays and slowed progress. An alternative is required now to reduce connection latency. The third dimension is used in popular 3D IC technology IC technology requires through silicon via (TSV) for signal integrity and heat mitigation. Noise coupling hinders electrical communication between signal-carrying TSVs (aggressive TSVs) and ground TSVs (victim TSVs), a 3D IC bottleneck. TSVs must be dielectrically insulated from Si substrates to avoid electrical signal interference. Additionally, first-order modelling will confirm the suggestions. This article proposes using the nanosheet field effect transistor (NSFET) to overcome 3D IC noise coupling and complementary metal oxide semiconductor (CMOS) technology nodes. After discussing the electronic industry and sub nm, several basic metrics and criteria for developing electronic components are presented. The first technique uses Perylene-N's exceptional noise-cancelling characteristics. Second technique uses electrical TSV (ETSV), thermal TSV (TTSV), and heat source models to measure noise coupling on numerous ICs. The third proposes many noise-reducing materials. The suggested structures outperform traditional approaches.</p>

Performance Analysis Using Air Gap Defected Through Silicon Via: Impact on Crosstalk and Power

In the recent past, various fabrication-related defects such as electromigration-induced open/short faults, interfacial cracks, and thermal stress-induced leakage problems in through silicon via (TSV) have a major impact on the reliability and performance of a TSV-based 3-D integrated circuit (IC). Considering these facts, this article for the first time provides the equivalent resistance-inductance-conductance-capacitance (RLGC) modeling and performance analysis of air gap-defected TSVs in comparison with defect free vertical interconnect at 7 nm technology in order to address reliability concerns. Considering different manufacturing imperfections such as air cracks and void holes, the analytical equations are derived using defective parameters to analyze the feasibility and reliability of defected TSVs. Using a driver-via-load (DVL) setup, an equivalent T-type electrical modeling of cylindrical TSV is proposed considering the impact of different forms of air-cracked defects. Therefore, the propagation delay, power dissipation, power delay product, peak noise, and dynamic crosstalk are analyzed using a carbon nanotube field effect transistor (CNTFET) driver. Encouragingly, considering a partial air-cracked TSV, the peak noise is improved by 4.83% approaching toward defect-free condition.

Equivalent thermal model of through silicon via and bump for advanced packaging of integrated circuits

Thermal issue is a quite critical factor in influencing the performance of integrated circuits (ICs) with the increase of the device integration density. Through silicon via (TSV) and bump have large significance in temperature analysis and thermal-aware physical optimizations in 2.5-D or 3-D ICs. In this paper, a new equivalent thermal model of TSVs and bumps is proposed to capture the anisotropic characteristics of the thermal conductivities of complicated structures and alleviate the computational expenses required for large-scale 3-D stacked chips or 2.5-D chiplet heterogeneous integration (CHI). The present equivalent model not only investigates the vertical direction conductivities of TSVs with insulating layer and bumps without insulating layer, but also incorporates the heat transfer effects of lateral direction in consideration of geometrical parameters. The equivalent method has been further extended to construct an equivalent thermal model of TSV and bump arrays to consider the anisotropic effects of thermal conductivities. The proposed model has been verified by comparing the calculated thermal conductivities with the results of finite element analysis (FEA). It is found that the simulation error of the present model is <2 % compared with the calculated FEA results. Furthermore, the influences of the design structures of TSVs and bumps on the thermal conductivities are also performed to validate the accuracy of the equivalent model and describe the primary factor impacting the thermal behavior of a 2.5-D or 3-D chip. Therefore, the consistency of the equivalent thermal model with FEA simulation indicates that the proposed equivalent TSV and bump model can be easily integrated into a thermal analysis framework to construct a more efficient thermal simulation tool to improve the accuracy of temperature distribution for CHI or 3-D ICs.

The Investigation of Electrical Characteristics for Carbon Nano-Tubes as Through Silicon Via in Multi-Layer Stacking Scheme With an Optimized Structure

Through silicon via (TSV) is the key technology for 3-D integrated circuits (3-DICs) which could vertically stack homogeneous or heterogeneous dies with the high performance and density. To evaluate the electrical characteristics of TSV at the high-frequency transmission, the skin effect and surface roughness effect are necessary to be considered. However, these effects would significantly result in the TSV equivalent resistance under the high operating frequency. Thus, it is important to investigate the carbon nano tubes (CNTs) TSV which has less skin effect intrinsically. In this work, we analyze the advantage of CNTs as TSV compared to the conventional filling materials such as copper (Cu). Furtherly, we also propose the equivalent circuit model of TSV and its multi-layer structure to simulate the electrical behaviors with different TSV pitch, height, diameter, and stacking layers by using ANSYS designer and high-frequency structure simulator (HFSS). Based on the frequency-domain analysis, it can be found that CNTs TSV has the lower frequency-dependent loss than Cu due to the lower equivalent resistance. In a summary, CNTs could be a promising TSV filling material at the high-speed transmission frequency based on our study.

Simplistic approach to alleviate noise coupling issues in 3D IC integration

Through-silicon-via (TSV) technology has emerged as the key technology to enable 3D IC integration. 3D integration is seen as the leading candidate, which can help in sustaining Moore’s Law to future IC technology nodes. It clearly set a benchmark to the IC industry due to its tremendous benefits in performance, data bandwidth, and supports heterogeneous integration. In 3D IC structure TSV’s are used to carry the overall electrical signal between the layers. The major drawback in the TSV based 3D integration is noise coupling between aggressive (electrical signal carrying TSV; ETSV) and victim TSV’s (ground). It can be reduced by creating very good isolation between TSV’s and Si substrate by using different liner materials around TSV’s. In this work, we have addressed various TSV models to reduce noise coupling between the TSV’s. The models we have studied are single layer model and stacked layers of liner model. Apart from this we have studied how the core materials in the TSV reduces noise coupling between aggressive and victim TSV’s. Also, we have shown the high frequency study for proposed models. Finally, our work shows single layer model with Crystalline-Germanium is comparably better noise coupling reduction even at higher frequency.

Fast and Accurate Power Distribution Network Modeling of a Silicon Interposer for 2.5-D/3-D ICs With Multiarray TSVs

In this paper, we first propose power distribution network (PDN) model of the perforated power and ground (P/G) planes including substrate effects and multiarray through-silicon vias (TSVs) for a silicon interposer. Since it is almost impossible to simulate a high metal density perforated PDN structure, we first suggest a modeling methodology for P/G perforated planes to reduce simulation time significantly with a high accuracy. To obtain the PDN impedance of a silicon interposer faster, we convert the perforated planes to solid planes with a dielectric mixture. The capacitance (C) and conductance (G) component of perforated P/G planes are precisely estimated based on the conformal mapping method. From the estimated C and G, the physical dimension and material properties of the dielectric mixture of solid P/G planes are determined, respectively. Because silicon interposer PDN consists of a periodic structure, we design and analyze the unit cell of a PDN thoroughly. From the unit cell analysis, the electrical characteristic of an entire PDN for a silicon interposer is successfully estimated. The PDN impedance of the proposed solid and perforated P/G planes and simulation time to obtain each PDN impedance are compared and evaluated, respectively. The proposed methodology is validated by a full 3-D electromagnetic (EM) simulation in the frequency range from 0.01 to 20 GHz. We also proposed models of multiarray P/G TSVs that can be applied to the various P/G patterns for a silicon interposer. From the inductance matrix considering current directions, the self- and mutual inductances of TSVs are accurately calculated. Because quasi-transverse electromagnetic mode is propagated through TSVs and the substrate dielectric of a silicon interposer can be regarded as a uniform dielectric, the capacitance and conductance of TSVs can be calculated from the inductance matrix. The proposed model of multiarray TSVs is also analyzed and verified by EM simulations in the frequency range from 0.01 to 20 GHz with a high accuracy.

High-Frequency Electrical Model of Through-Silicon Vias for 3-D Integrated Circuits Considering Eddy Current and Proximity Effects

A novel $\pi $ -type equivalent-circuit model of through-silicon vias (TSVs) for 3-D integrated circuits (3-D ICs) considering eddy current and proximity effects is proposed in this paper. The numerical models for the serial resistance and inductance of TSVs are derived by computing the longitudinal electrical field in Cu and the longitudinal magnetic vector potentials in SiO2 and Si substrate with Fourier-Bessel series. Furthermore, the closed-form formulas for the parallel capacitance and conductance of TSVs are derived by using the conformal mapping method. The proposed $\pi $ -type equivalent-circuit model is verified using 3-D full-wave field solver High-Frequency Structural Simulator, showing that it is highly accurate up to 100 GHz. Using the proposed model, the electrical performance of TSVs with high density can be evaluated accurately and quickly in a wideband frequency range.

An Accurate and Fast Substrate Noise Prediction Method With Octagonal TSV Model for 3-D ICs

In this paper, a refined equivalent circuit model considering semiconductor effect of 3-D ICs is proposed based on three-dimensional transmission line matrix method. In the proposed model, the depletion region around a through silicon via (TSV) is modeled as distributed voltage-dependent capacitors and resistors. With the proposed model, noise behaviors could be accurately obtained under relatively short simulation time when compared to the time needed by full wave simulators. The simulation result of the proposed model is aligned with both ANSYS HFSS and TCAD Sentaurus in frequency and time domains while the simulation time is greatly reduced to less than 1%. The influence of TSV-induced substrate noise on an active circuit is demonstrated using the proposed model. The CMOS inverter affected by the noisy substrate shows up to 34-mV deviation at the inverter output when compared to the inverter on a noise-free substrate.

High-Frequency Electrical Modeling and Characterization of Differential TSVs for 3-D Integration Applications

This letter makes a fast and efficient analysis of the scalable differential through-silicon via (TSV) configuration in 3-D integrated circuits. The equivalent-circuit model of a differential TSV pair is described. The critical differential characteristics are analyzed and calculated in terms of a lumped-circuit model and the effective loop parameters of multi-TSVs. The calculated results are validated by the 3-D full-wave field solver high frequency simulator structure (HFSS) over a wide frequency range.

Plastic analysis for through silicon via with actual etching defect of triangular-teeth and scallops

Through silicon via (TSV) with triangular-teeth and scalloped side wall (TSSW) not only lowers down the electrical performance but also alters the mechanism of thermal mechanical stability. By considering the realistic etching defects on TSV side wall, a more reasonable and reliable three-dimension (3D) TSV model with TSSW is built. The thermo-mechanical issues induced by the unsmooth side wall of the TSV are studied by finite element method (FEM) in this work. With the presence of TSSW, much more tips in interfaces of the TSV-Cu and SiO2 and the SiO2 and Si are brought and the shear stress and normal stress are distinct comparing with the smooth side wall. Therefore, the thermo-mechanical mechanism of the TSV is changed greatly. By investigating the normal stress, shear stress and strain energy density (SED) of the triangular-teeth local region, it has been found that severe normal stress variation (−200–70MPa) and multiple variation of shear stress τxy contributes the peeling, slip and crack issues. The effective plastic strain, displacement and von Mises stress, and shear stress and normal stress in the X, Y and Z direction are studied in detail. The effect of the TSSW on the thermal stress and keep-out zone (KOZ) size is discussed.

Modeling and Optimization of Multiground TSVs for Signals Shield in 3-D ICs

This paper presents an effective loop impedance extraction method and a model of a signal through-silicon via (TSV) surrounded by multiground TSVs. According to this method, the effective coupling substrate capacitances of multiground TSVs with different numbers and placements are calculated. Based on the calculated values of the resistance-inductance-capacitance-conductance (RLCG) parameters, the equivalent circuit and a two-port network model are established. The S -parameters of the model are validated by the simulated and measured results. Then, the effect of different patterns of ground TSVs on the central signal and coupling capacitance are discussed. Note that the hexagon pattern proposed in this paper can save the occupied area prominently without damaging the signal integrity.

Effects of dimension parameters and defect on TSV thermal behavior for 3D IC packaging

Through Silicon Via (TSV) technology is a promising and preferred way to realize the reliable interconnection for 3D IC integration. The temperature changed in the processes of TSV manufacturing and chip using, due to the mismatch in the Coefficient of Thermal Expansion (CTE) of the materials used in TSV structure, significant thermal stress will be induced under the thermal load. These stresses may lead to various reliability issues. Dimension parameters and defects are the two factors affecting the thermal behavior of TSV. In order to optimize TSV design and the quality of via filling, a numerical model of Cu-filled TSV was established to simulate and analyze the effect of diameter, aspect ratio (AR) and defects on TSV thermal stress and deformation in this paper. Simulation results show that the equivalent stress and total deformation of TSV increases as the increase of the diameter of TSV. The effect of aspect ratio on equivalent stress is very little; however, it has a great impact on total deformation, especially for the large diameter of the TSV. Additionally, the effects of shape, size and location of defect on thermal stress were also investigated.

Numerical modeling and experimental verification of copper electrodeposition for through silicon via (TSV) with additives

Since voids and seams are easily formed during the process of filling TSVs with high aspect ratio, good methods that can achieve the superfilling of TSVs are eagerly needed. This paper presents the numerical modeling of TSV filling concerning the influence of three additives (accelerator, suppressor and leveler). By changing the additives' doses and current density, the following three different simulation results were obtained: the pinch-off effect, seam-inside filling model and “V” shaped filling model. The corresponding distributions of the current density along the cathode surface were analyzed to investigate the filling mechanism. Moreover, TSV filling experiments in the presence of additives were also conducted to validate the proposed numerical model. The simulation results matched well with the experimental results. TSVs with a diameter of 20μm and depth of 200μm were fully filled in the appropriate conditions.

Noise Coupling Models in Heterogeneous 3-D ICs

Models of coupling noise from an aggressor module to a victim module by way of through silicon vias (TSVs) within heterogeneous 3-D integrated circuits (ICs) are presented in this paper. Existing TSV models are enhanced for different substrate materials within heterogeneous 3-D ICs. Each model is adapted to each substrate material according to the local noise coupling characteristics. The 3-D noise coupling system is evaluated for isolation efficiency over frequencies of up to 100 GHz. Isolation improvement techniques, such as reducing the ground network inductance and increasing the distance between the aggressor and victim modules, are quantified in terms of noise improvements. A maximum improvement of 73.5 dB for different ground network impedances and a difference of 38.5 dB in isolation efficiency for greater separation between the aggressor and victim modules are demonstrated. Compact, accurate, and computationally efficient models are extracted from the transfer function for each of the heterogeneous substrate materials. The reduced transfer functions are used to explore different manufacturing and design parameters to evaluate coupling noise across multiple 3-D planes.

Experimental Stress Characterization and Numerical Simulation for Copper Pumping Analysis of Through-Silicon Vias

In this paper, a 3-D thermomechanical model of through-silicon vias (TSVs) has been analyzed and verified with in situ microscale strain measurements by synchrotron X-ray microdiffraction. Thereafter, a comprehensive stress/strain analysis on copper pumping and back-end-of-line (BEOL) cracking issues has been carried out. In addition, a design-of-experiments-based approach has been used to understand the effect of various parameters on copper pumping and BEOL stress. The results show that the smaller TSV diameter and thinner silicon die help reduce the copper pumping and thus mitigate BEOL stress.

High-Frequency Analysis of Cu-Carbon Nanotube Composite Through-Silicon Vias

A high-frequency analysis of Cu-carbon nanotube (CNT) composite through-silicon vias (TSVs) is conducted. The electrical modeling of the Cu-CNT composite TSVs is performed, with the effective complex conductivity formulated for accurate characterization of kinetic inductance. It is shown that, after codepositing CNT with Cu, the electrical conductivity of the TSVs can be improved and the influence of kinetic inductance variation can be suppressed in comparison with the CNT TSVs. On the other hand, the Cu-CNT composite TSVs can exhibit little compromise in performance yet much enhanced reliability by comparison to the Cu counterpart. That is, the Cu-CNT composite TSVs can provide a better tradeoff between reliability and performance than the Cu and CNT counterparts.

An Analytical Capacitance Model for Through-Silicon Vias in Floating Silicon Substrate

Through-silicon via (TSV) is an integral part of 2.5-D IC technology leveraged for multichip heterogeneous integration to achieve shorter interconnects, faster speed, and lower power consumption in the state-of-the-art circuit systems. These 2.5-D ICs use a silicon substrate, where there are no ground contacts unlike traditional 2-D ICs or 3-D ICs. TSVs in such electrically floating substrates call for new electrical models as well as improved parasitic extraction (PEX) methodology. Therefore, in this paper, an analytical capacitance model for TSVs in a 2.5-D IC is derived and validated. A TSV-to-TSV crosstalk expression is also validated and further extended to create an accurate 2.5-D IC PEX framework in addition to design robust grounding schemes, such that the TSV-to-TSV crosstalk coupling in an entire 2.5-D IC would be minimal even with floating silicon substrate. It is shown that a large number of regularly distributed power and ground TSVs provide an effective shield for the TSV-to-TSV crosstalk coupling and are highly recommended in the 2.5-D ICs.

A Rigorous Approach for the Modeling of Through-Silicon-Via Pairs Using Multipole Expansions

This paper presents a novel multipole expansion method for the rigorous analysis of wave propagation along a through-silicon-via (TSV) pair. TSV models are often constructed using equivalent circuits under the assumption that the interfaces between different media are equipotential. In comparison with that, the proposed method is a rigorous full-wave solution of the propagation mode. It takes advantage of cylindrical wave expansion functions and matches the boundary conditions at both the metal-to-insulator and insulator-to-silicon interfaces exactly. The method is validated against a full-wave finite-element method solver, and analysis examples using the method are demonstrated in a frequency range up to 100 GHz.

An Analytical Through Silicon Via (TSV) Surface Roughness Model Applied to a Millimeter Wave 3-D IC

In the millimeter wave (mmW) frequency range, the root mean square height of the through silicon via (TSV) sidewall roughness is comparable to the skin depth, and hence, becomes a critical factor for TSV modeling and analysis. In this paper, the impact of the TSV sidewall roughness on electrical performance, such as the loss and impedance alteration in the mmW frequency range, is examined and analyzed. The second-order small analytical perturbation method is applied to obtain a simple closed-form expression for the power absorption enhancement factor of the TSV. In this study, we propose an electrical model of the TSV, which considers the TSV sidewall roughness effect, the skin effect, and the metal oxide semiconductor effect. The parameters of the proposed circuit model can be determined analytically; the accuracy of the model is validated through a comparison of circuit model behavior for full wave electromagnetic field simulations up to 100 GHz.