Abstract
In this paper, a refined equivalent circuit model considering semiconductor effect of 3-D ICs is proposed based on three-dimensional transmission line matrix method. In the proposed model, the depletion region around a through silicon via (TSV) is modeled as distributed voltage-dependent capacitors and resistors. With the proposed model, noise behaviors could be accurately obtained under relatively short simulation time when compared to the time needed by full wave simulators. The simulation result of the proposed model is aligned with both ANSYS HFSS and TCAD Sentaurus in frequency and time domains while the simulation time is greatly reduced to less than 1%. The influence of TSV-induced substrate noise on an active circuit is demonstrated using the proposed model. The CMOS inverter affected by the noisy substrate shows up to 34-mV deviation at the inverter output when compared to the inverter on a noise-free substrate.
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