Simulation Methodology and Evaluation of Through Silicon Via (TSV)-FinFET Noise Coupling in 3-D Integrated Circuits

Abstract

Bulk FinFETs have emerged as the solution to short-channel effects at the 22-nm technology node and beyond. The capability of 3-D stacking of dies from various technologies will eventually enable stacking FinFET dies within 3-D integrated circuits. Within 3-D circuits, through silicon vias (TSVs) are a known source of substrate noise in planar bulk technologies. While FinFETs are expected to demonstrate superior noise immunity relative to planar devices due to superior gate control over and volume inversion of the active fin, the impact of TSV noise on FinFETs has not been previously quantified. To evaluate TSV-FinFET noise coupling, we develop in this paper a simulation methodology that extends the state of the art by accurately modeling substrate noise due to digital signals on nearby TSVs and improving the extraction of substrate circuit models from full-wave electromagnetic simulations. To overcome the lack of high-fidelity FinFET SPICE models that accurately capture the effects of substrate noise, we use high-fidelity technology computer-aided design (TCAD) FinFET models. Our results show that FinFETs exhibit an order of magnitude less leakage current noise transients, and two orders of magnitude less saturation current noise transients, relative to comparable planar technologies. Our findings are generalizable, showing that FinFETs are significantly more robust to substrate noise than equivalent planar devices.