Interfacial Delamination Between Through Silicon Vias (TSVs) and Silicon Matrix

Abstract

Recently, three-dimensional (3-D) integration with through silicon vias (TSVs) has emerged as an effective solution for interconnect structures beyond the 32-nm technology node in microelectronics. Among others, thermo-mechanical reliability is a key concern for the development of TSV structures used in 3-D interconnects. This paper examines the thermal stress-induced delamination between through silicon via (TSV) and the silicon matrix. First, the driving force for TSV delamination was derived for a long crack at the steady state, and then the analytical solutions were validated using finite element analysis (FEA). The analytical solutions and simulation results were found to be in good agreement at the steady state, and together they suggested a fracture mechanism to account for the TSV delamination observed. The analytical solution further provided a basic framework for studying the impact of materials, process and structural design on reliability of the TSV structure. In particular, we found that reducing the thermal mismatch and TSV diameter yield definite advantages in lowering the crack driving force for TSV delamination. Such driving force can also be controlled by introducing an annular metal filling or a dielectric liner between TSV and the Si matrix. Finally, the TSV protrusion phenomenon during thermal cycles was investigated. The interfacial delamination was found to initiate during a cooling process and to develop under a subsequent heating process, causing TSVs to protrude from the silicon matrix after repeated thermal cycles.