TSV Extracted Equivalent Circuit Model and an On-Chip Test Solution

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Through silicon via (TSV) is the enabling technology for 3-D integrated circuit (IC) realization. To develop manufacturing tests for 3-D ICs, TSV has to be accurately modeled. Analytical methods are commonly used to develop circuit models for TSVs. These models are often difficult to develop and require some assumptions to simplify the problem. This paper presents a new method utilizing computer-aided design tools to extract circuit models for prebond and postbond TSVs. It is shown how the effects of common TSV parametric and catastrophic faults such as pinholes, voids, and open circuits affect TSV circuit models through 3-D full-wave simulations. It is also shown that the substrate conductivity has a considerable effect on the TSV fault characterization. The extracted models indicate that even a relatively large void does not alter the TSV characteristic parameters and thus voids remain largely undetected with conventional test solutions. An on-chip circuit, utilizing a delay-locked loop is presented as a test solution to detect TSV parametric faults.