Virtualization-Based Efficient TSV Repair for 3-D Integrated Circuits

Muhammad Imran,Taehyun Kwon,Jooho Kim,Joon-Sung Yang,Hyunseung Han,Jaeyong Chung

doi:10.1109/access.2019.2940211

Abstract

Three-dimensional (3-D) integration offers a promising solution to the technology scaling barriers. Reliability of the 3-D Integrated Circuits (ICs) is highly dependent on the integrity of the underlying interconnect. Through Silicon Via (TSV) based 3-D ICs would suffer from low yield due to the faults in TSVs. In addition, TSVs introduce stress and noise in the substrate. Adding redundant TSVs for repairing the faulty ones has commonly been proposed to improve the yield of TSV-based 3-D ICs. The existing TSV repair approaches employ a number of spare TSVs in a group of signal TSVs. We propose a TSV virtualization based repair architecture which utilizes a single redundant TSV to repair multiple faulty TSVs. The proposed architecture relies on transmitting multiple bits through a single TSV using multi-level voltage quantization. It makes efficient use of the TSV redundancies in repairing the faulty TSVs. With less number of spare TSVs, the proposed architecture can reduce the area overhead by more than 70%. Reduction in the TSV count allows greater interconnect density and helps to mitigate the TSV-induced noise and stresses. Alternatively, for a similar number of spare TSVs, the proposed method can enhance the fault tolerance capability of the conventional approaches thus leading to an enhanced chip yield. The eye diagram simulations using an electrical model of the TSV show a reduction of less than 5% in noise margin when using a 16-level voltage quantization at a data rate of 5 Gbps which is typical for 3-D integration applications.

Highlights

Semiconductor device scaling is aimed at performance enhancement by reducing the interconnect delays, increasing density and decreasing power dissipation [1]
EVALUATION We use eye diagram simulations to confirm the viability of the proposed architecture and to analyze the reduction in signal noise margin by the proposed multi-level voltage quantization
We evaluate the various aspects such as yield, number of Through Silicon Via (TSV) and area overhead for the proposed method compared to the conventional TSV repair approaches

Summary

INTRODUCTION

Semiconductor device scaling is aimed at performance enhancement by reducing the interconnect delays, increasing density and decreasing power dissipation [1]. Variations, tunneling current leakage, increasing parasitics and interconnect power dissipation constraints [2], [3] These limitations are hampering the continuation of the technology scaling trend. The fabrication of TSVs requires additional components such as landing pads and bumps All these factors limit the overall number and density of the TSVs. TSVs are vulnerable to several faults introduced during the manufacturing process. The existing TSV repair architectures use multiple redundant TSVs to replace the faulty ones. The proposed architecture offers a low cost and efficient TSV repair solution while reducing the overall TSV count, allowing greater interconnect density. Compared to the existing TSV repair architectures, the proposed architecture is efficient in utilizing the spare TSVs and requires less area overhead.

PREVIOUS WORKS

EVALUATION

CONCLUSION