Parametric thermal analysis of TSVs in a 3-D module based on interconnect delay and silicon efficiency

Abstract

The convergence and miniaturization of the consumer electronic products such as cell phones and digital cameras has led to the vertical integration of packages i.e., 3-D packaging. 3-D chip stacking is emerging as a powerful tool that satisfies such Integrated Circuit (IC) package requirements. 3-D technology is the trend for future electronics, especially hand-held, hence, making it an important research area. Due to high package density and chip-stacking on top of each other, heat dissipation from the stacked chips becomes a concern. To overcome these thermal challenges and provide better inter-chip and chip-substrate electrical connection, Through Silicon Via (TSV) technology is being implemented in 3-D electronics. TSV is one of the key enabling technologies for 3-D systems. TSVs allow 3-D chips to be interconnected directly and provide high speed signal processing. Electrical interconnection and heat dissipation improves with the number of TSVs. But, there is a trade-off; silicon efficiency of a 3-D package decreases with the TSV count. There are studies for thermo-mechanical analysis of TSVs both at wafer and package level but there is limited data on the electrical aspects of TSVs, i.e., effect of TSV temperature and layout/size on the interconnect delay. In this paper, interconnect delay is determined for various TSV configurations at the package level. Interconnect delay is primarily driven by the interconnect size and temperature. The objective of this work is to determine the optimal number/size of TSVs as a function of silicon efficiency, junction temperature and the interconnect delay. Chip real estate (CRE) - actual chip area available to lay down devices, is varied from 98% to 96% with an interval of 2% (2 cases). For each CRE case, sub-cases are formulated by varying the TSV count/size (keeping the CRE constant) and chip temperature and the interconnect delay is determined and compared. It is seen that for all the TSV configurations at constant CRE, the junction temperature remains constant, however the interconnect delay varies significantly. The work provides design guidelines based on CRE, junction temperature and the interconnect delay for varied applications in the electronics industry.