Gate Capacitance Model Research Articles

Voltage- and temperature-dependent gate capacitance and current model: application to ZrO/sub 2/ n-channel MOS capacitor

Based on the energy-dispersion relation in each region of the gate-dielectric-silicon system, a tunneling model is developed to understand the gate current as a function of voltage and temperature. The gate capacitance is self-consistently calculated from Schrodinger and Poisson equations subject to the Fermi-Dirac statistics, using the same band structure in the silicon as used for tunneling injection. Franz two-band dispersion is assumed in the dielectric bandgap. Using a Wentzel-Kramer-Brillouin (WKB)-based approach, direct and Fowler-Nordheim (FN) tunneling and thermionic emission are considered simultaneously. The model is implemented for both the silicon conduction and valence bands and both gate- and substrate-injected currents. ZrO/sub 2/ NMOSFETs were studied through temperature-dependent C/sub g/-V/sub g/ and I/sub g/-V, simulations. The extracted band gaps and band offsets of the ZrO/sub 2/- and interfacial-Zr-silicate-layer are found to be comparable with the reported values. The gate currents in ZrO/sub 2/-NMOSCAPs are found to be primarily contributed from the silicon conduction band and tunneling appears to be the most probable primary mechanism through the dielectric. Oscillations of gate currents and kinks of gate capacitance were observed near the flat-band in the experiments. These phenomena might be caused by the interface states.

A comparison of wave-function penetration effects on gate capacitance in deep submicron n- and p-MOSFETs

We have calculated the effects of wave function penetration into the gate-oxide on the modeling of gate capacitance in deep submicron p-MOSFETs on [100] silicon for the first time. These results are compared to those of n-MOSFETs. Self-consistent calculations show that contrary to the common belief, penetration effects are more pronounced in p-MOS devices. The error in inversion capacitance due to neglect of penetration effects has opposite dependence on substrate doping density for n-MOS and p-MOS structures. Consequently, the error in gate capacitance for an n-MOSFET in strong inversion is strongly dependent on doping density, while that for a p-MOSFET essentially does not depend on doping density. An explanation for this unusual result is also provided. Although the error in gate capacitance is only a few percent, it will have nontrivial effects on device parameter extraction from capacitance-voltage (C-V) measurements.

A new model of gate capacitance as a simple tool to extract MOS parameters

This paper tackles the difficult task to extract MOS parameters by a new model of the gate capacitance that takes into account both poly-Si depletion and charge quantization and includes temperature effects. A new fast and iterative procedure, based on this simplified self-consistent model, will be presented to estimate simultaneously the main MOS system parameters (oxide thickness, substrate, and poly-Si doping) and oxide field, surface potentials at the Si/SiO/sub 2/ and at the poly-Si/SiO/sub 2/ interfaces. Its effectiveness will be demonstrated by comparing oxide field and oxide thickness to those extracted by other methods proposed in the literature. Moreover, these methods are critically reviewed and we suggest improvements to reduce their errors. The agreement between CV simulation and experimental data is good without the need of any free parameter to improve the fitting quality for several gate and substrate materials combinations. Finally, a simple law to estimate substrate and poly-Si doping in n/sup +//n/sup +/ MOS capacitors from CV curves is proposed.

Surface layer effective density-of-states (SLEDOS) and its applications in MOS devices modeling

The concept of surface potential effective density-of-states (SLEDOS) is presented in modeling the quantized inversion layer. Carrier distribution models both in semi-classical and quantum mechanical cases are developed based on SLEDOS. Threshold voltage shift model due to QMEs, a new iteration method to calculate the inversion carrier sheet density and surface potential, as well as a gate capacitance model are built based on the concept of SLEDOS. It is demonstrated that the concept of SLEDOS reveals the physical nature of inversion layer quantization and provides a feasible method to characterize MOS inversion layer.

Modeling of MOS scaling with emphasis on gate tunneling and source/drain resistance

Two critical aspects of the MOS scaling towards sub-100 nm gate length are addressed: the gate tunneling and capacitance modeling, and optimization of shallow source/drain (S/D) extension junction to minimize the series resistance. Both advanced physics (quantum mechanics or QM) and practical solution (circuit simulation) are used to tackle the modeling approach. Good results have been obtained compared to available experimental data, validating the hierarchical methodology used in this paper. A hybrid, semi-analytical QM model for channel carrier profile and an accurate direct tunneling model have been developed. An nMOS transistor with effective channel length of 0.08 micron has been analyzed to demonstrate the methodology proposed.

A new model of switching operation in fully depleted ultrathin-film CMOS/SIMOX

An analysis is made of the switching performances of fabricated ultrathin-film submicrometer-gate CMOS/SIMOX ring oscillators. A time-dependent gate capacitance model is proposed to explain the switching operation mechanism. It is found that reducing the gate capacitance by full depletion of the body silicon dramatically improves the propagation delay time of CMOS/SIMOX.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An accurate model for power DMOSFETs including interelectrode capacitances

A SPICE-compatible circuit model for power MOSFETs is presented. It is based on device physics and uses a subcircuit representation. The interelectrode capacitances are modeled accurately as nonlinear functions of the applied biases. Various second-order effects relating to the gate capacitance model are discussed, and strategies are presented to include them in the model. The model parameters can be obtained from device measurements. The model is verified by comparing measured and simulated waveforms from a gate charge test circuit.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Characterization of the inverse-narrow-width effect

The inverse-narrow-width effect, the reduction in the threshold voltage with decreasing device width, is modeled and experimentally measured. A fringing gate capacitance model is extended to include the effects of the sidewall interface charge. Two- and three-dimensional simulations are used to illustrate the enhanced sidewall potential and current, and the effect of sidewall interface charge on the electrical behavior of MOSFET's with fully recessed isolation oxides. We compare the closed-form analytical threshold voltage expression developed with experimental data from small-geometry NMOS devices and find very good agreement.