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Abstract
A SPICE-compatible circuit model for power MOSFETs is presented. It is based on device physics and uses a subcircuit representation. The interelectrode capacitances are modeled accurately as nonlinear functions of the applied biases. Various second-order effects relating to the gate capacitance model are discussed, and strategies are presented to include them in the model. The model parameters can be obtained from device measurements. The model is verified by comparing measured and simulated waveforms from a gate charge test circuit.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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