Abstract

The inverse-narrow-width effect, the reduction in the threshold voltage with decreasing device width, is modeled and experimentally measured. A fringing gate capacitance model is extended to include the effects of the sidewall interface charge. Two- and three-dimensional simulations are used to illustrate the enhanced sidewall potential and current, and the effect of sidewall interface charge on the electrical behavior of MOSFET's with fully recessed isolation oxides. We compare the closed-form analytical threshold voltage expression developed with experimental data from small-geometry NMOS devices and find very good agreement.

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