Μm SOI CMOS Technology Research Articles

Исследование и оптимизация по критерию сбоеустойчивости ячейки памяти для технологии КНИ КМОП 0,25 мкм при облучении быстрыми нейтронами

Исследование и оптимизация по критерию сбоеустойчивости ячейки памяти для технологии КНИ КМОП 0,25 мкм при облучении быстрыми нейтронами

15158A SP6T RF switch based on IBM SOI CMOS technology**Project supported by the Zhejiang Provincial Natural Science Foundation of China (No. LZ16F010001).

This paper presents the design of single-pole six-throw (SP6T) RF switch with IBM 0.18 μm SOI CMOS technology, which can be widely used in a wireless communication system with its high performance and low cost. The circuit is designed and simulated by using an idea that the total load is divided into six branches and SOI special structures. The insertion loss is less than 0.6 dB, isolation is more than 30 dB, the input power P0.1dB for 0.1 dB compression point is more than 37.5 dBm, IIP3 is more than 70 dBm, the 2nd and the 3rd harmonic compressions are more than 96 dBc, and the control voltage is (+2.46 V, 0, −2.46 V) in the frequency from 0.1 to 2.7 GHz.

Operation of thin-film gated SOI lateral PIN photodetectors with gate voltage applied and intrinsic length variation

This paper describes the operation principle of thin-film gated SOI lateral PIN photodetectors, and an analytical model of depletion voltage is presented and validated by two-dimensional Atlas simulations. With gate voltage applied to achieve fully depleted (FD) condition in intrinsic region, the variation of intrinsic length (Li) on photocurrent and dark current characteristics, sensitivity, and speed is addressed. With Li between 1 and 10μm, the simulated results predict internal quantum efficiency (QI) in excess of 95% even near 100% at a 400nm wavelength. Also, QI can yield over 87% for the long channels. Under FD condition, the total −3dB frequency value can achieve 16GHz (19GHz) for Li=1 and 4.1GHz (6.2GHz) for Li=2μm with VK=1.0V (2.0V). And a high ratio of more than 107 between illuminated and dark currents can be yielded for all detectors realized in 0.18μm SOI CMOS technology.

Continuous Acquisition Pixel 12: General Overview of Design

Abstract The next generation of vertexing detectors in collider experiments will require order of magnitude increases in readout speed and increased background rates. The CAP12 continues the evolution of a number of binary, 3T based pixel detector related technologies at the University of Hawaii (UH) to address readout speed, density requirements, and background rate issues. The CAP12 takes the HIXEL (Hexagonal Pixels) readout method developed at UH and combines it with faster digital logic, column based threshold biasing, and manufactured on a 0.2 μm SOI CMOS technology. Pixel size has been reduced to 30 μm by 30 μm and on die threshold DACs are intended to improve analog performance and biasing. The chip architecture is presented as well as simulations and preliminary results.

Comparison of Digital to Analog Converters in 0.20μm SOI and 0.13μm CMOS Process

Abstract Biasing and threshold adjustments are crucial for the correct operation and sensitivity of 3T based pixel detectors. The latest generation of pixel detectors detectors designed at the University of Hawaii (UH) have adjustable triggering thresholds by including on chip 8-bit R-2R Digital to Analog Converters (DAC). The DAC is the first designed at UH to be manufactured in a 0.20 μm SOI CMOS technology. The DAC has additionally been fabricated in a 0.13 μm CMOS technology. The inclusion of such structure allows comparison between fabrication runs as well as fabrication technologies. Simulations and preliminary results are included, as well as comparisons between fabrication technologies.

Analysis and optimization of lateral thin-film Silicon-on-insulator (SOI) MOSFET transistors

This paper is focused on the analysis and optimization of power N-type LDMOS (LDNMOS) transistors (VBR>120V) with the purpose of being integrated in a new generation of Smart-Power technology based upon a 0.18μm SOI-CMOS technology. The influence of some important design parameters such as the shallow trench isolation (STI) length (LSTI), the N-well doping profile and the relative position of the N-well mask to the STI block are analyzed in terms of voltage capability (VBR), specific on-state resistance (Ron-sp) and electrical safe-operating area (SOA) by means of Technology Computer-Aided Design (TCAD) numerical simulations. The evolution of the measured and simulated VBR as a function of the substrate (handle wafer) voltage (HWV) gives good physical insight of the optimal LDNMOS drift region design configuration. LDNMOS transistors with STI lengths partially covering the drift region length leads to better combined action of Ron-sp/VBR trade-off and electrical SOA results.

Analysis and optimisation of lateral thin-film silicon-on-insulator (SOI) PMOS transistor with an NBL layer in the drift region

This paper analyses the experimental results of voltage capability (VBR>120V) and output characteristics of a new lateral power P-channel MOS transistors manufactured on a 0.18μm SOI CMOS technology by means of TCAD numerical simulations. The proposed LDPMOS structures have an N-type buried layer (NBL) inserted in the P-well drift region with the purpose of increasing the RESURF effectiveness and improving the static characteristics (Ron-sp/VBR trade-off) and the device switching performance. Some architecture modifications are also proposed in this paper to further improve the performance of fabricated transistors.

Design and optimization of high voltage LDMOS transistors on 0.18 μm SOI CMOS technology

This paper analyses the voltage capability of lateral power ( V BR > 120 V) P- and N-channel MOS transistors manufactured on a 0.18 μm SOI CMOS technology by means of TCAD numerical simulations. The measured breakdown voltage results as a function of the handle wafer voltage of power LDMOS transistors are compared with TCAD numerical simulation with the purpose of understanding the problems arising in the measured structures. Some important design parameters such as the STI length ( L STI) and technological concerns like the P-well and N-well doping profiles have a strong influence on the voltage capability. As a consequence, some design solutions are proposed in this work to improve the performances of the fabricated LDMOS structures.

Design and optimization of different P-channel LUDMOS architectures on a 0.18 µm SOI-CMOS technology

This paper focuses on the design and optimization of different power P-channel LDMOS transistors (VBR > 120 V) to be integrated in a new generation of smart-power technology based upon a 0.18 µm SOI-CMOS technology. Different drift architectures have been envisaged in this work with the purpose of optimizing the transistor static (Ron-sp/VBR trade-off) and dynamic (Ron × Qg) characteristics to improve their switching performance. Conventional single-RESURF P-channel LUDMOS architectures on thin-SOI substrates show very poor Ron-sp/VBR trade-off due to their low RESURF effectiveness. Alternative drift configurations such as the addition of an N-type buried layer deep inside the SOI layer or the application of the superjunction concept by alternatively placing stacked P- and N-type pillars could highly improve the RESURF effectiveness and the P-channel device switching performance.

Analysis and optimization of safe-operating-area of LUDMOS transistors based on 0.18 µm SOI CMOS technology

This paper is focused on the design and optimization of power LDMOS transistors (VBR > 120 V) with the purpose of integrating them with a new generation of smart-power technology based upon 0.18 µm SOI-CMOS technology. Different LDMOS design structures with optimal /VBR trade-off have been analyzed in order to compare their electrical safe-operating-area (SOA). The influence of some important design parameters such as the STI length (LSTI) and technological concerns such as the P-well and N-well mask position distance is also exhaustively analyzed in this work.

Fully integrated blue/UV SOI CMOS photosensor for biomedical and environmental applications

In this paper, we present a microsystem for measuring optical power in blue/UV wavelengths (from ? = 200 nm to ? = 450 nm) which includes a photodiode and the analog processing circuit of the photodiode signal, fully integrated in 2 μm SOI CMOS technology. The photodiode has a maximum responsivity for ? = 400 nm. Th photosensor functions as a current to frequency converter. Measurements of the microsystem illuminated by blue and UV LEDs demonstrate the good linear behavior, sensitivity and efficiency of the system.

Effect of total ionizing dose radiation on the 0.25 μm RF PDSOI nMOSFETs with thin gate oxide

Thin gate oxide radio frequency (RF) PDSOI nMOSFETs that are suitable for integration with 0.1 μm SOI CMOS technology are fabricated, and the total ionizing dose radiation responses of the nMOSFETs having four different device structures are characterized and compared for an equivalent gamma dose up to 1 Mrad (Si), using the front and back gate threshold voltages, off-state leakage, transconductance and output characteristics to assess direct current (DC) performance. Moreover, the frequency response of these devices under total ionizing dose radiation is presented, such as small-signal current gain and maximum available/stable gain. The results indicate that all the RF PDSOI nMOSFETs show significant degradation in both DC and RF characteristics after radiation, in particular to the float body nMOS. By comparison with the gate backside body contact (GBBC) structure and the body tied to source (BTS) contact structure, the low barrier body contact (LBBC) structure is more effective and excellent in the hardness of total ionizing dose radiation although there are some sacrifices in drive current, switching speed and high frequency response.

Improved generation lifetime model for the electrical characterization of single- and double-gate SOI nMOSFETs

This work proposes a refined technique for the extraction of the generation lifetime in single- and double-gate partially depleted SOI nMOSFETs. The model presented in this paper, based on the drain current switch-off transients, takes into account the influence of the laterally non-uniform channel doping, caused by the presence of the halo implanted region, and the amount of charge controlled by the drain and source junctions on the floating body effect when the channel length is reduced. The obtained results for single-gate (SG) devices are compared with two-dimensional numerical simulations and experimental data, extracted for devices fabricated in a 0.1 µm SOI CMOS technology, showing excellent agreement. The improved model to determine the generation lifetime in double-gate (DG) devices beyond the considerations previously presented also consider the influence of the silicon layer thickness on the drain current transient. The extracted data through the improved model for DG devices were compared with measurements and two-dimensional numerical simulations of the SG devices also presenting a good adjustment with the channel length reduction and the same tendency with the silicon layer thickness variation.

Monolithically integrated 10 Gbit/s photodiode and transimpedance amplifier in thin-film SOI CMOS technology

The first monolithically integrated photodiode and transimpedance amplifier in ultra-thin-film SOI technology for 10 Gbit/s short-distance optical communication is presented. Results indicate performances compatible with the application, at very low power consumption, chip area and cost, using an all-silicon receiver in a 0.13 µm SOI CMOS technology.

The temperature mobility degradation influence on the zero temperature coefficient of partially and fully depleted SOI MOSFETs

The zero temperature coefficient (ZTC) is investigated experimentally in partially (PD) and fully depleted (FD) SOI MOSFET fabricated in a 0.13μm SOI CMOS technology. A simple model to study the behavior of the gate voltage at ZTC (VZTC) is proposed in the linear and the saturation region. The influence of the temperature mobility degradation on VZTC is analyzed for PD and FD devices. Experimental results show that the temperature mobility degradation is larger in FD than in PD devices, which is responsible for the VZTC decrement observed in FD instead of the increment observed in PD devices when the temperature increases. The analysis takes into account temperature dependence model parameters such as threshold voltage and mobility. The analytical predictions are in very close agreement with experimental results in spite of the simplification used for the VZTC model as a function of temperature in the linear and the saturation region.