Abstract
This paper is focused on the design and optimization of power LDMOS transistors (VBR > 120 V) with the purpose of integrating them with a new generation of smart-power technology based upon 0.18 µm SOI-CMOS technology. Different LDMOS design structures with optimal /VBR trade-off have been analyzed in order to compare their electrical safe-operating-area (SOA). The influence of some important design parameters such as the STI length (LSTI) and technological concerns such as the P-well and N-well mask position distance is also exhaustively analyzed in this work.
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