Abstract
This paper is focused on the analysis and optimization of power N-type LDMOS (LDNMOS) transistors (VBR>120V) with the purpose of being integrated in a new generation of Smart-Power technology based upon a 0.18μm SOI-CMOS technology. The influence of some important design parameters such as the shallow trench isolation (STI) length (LSTI), the N-well doping profile and the relative position of the N-well mask to the STI block are analyzed in terms of voltage capability (VBR), specific on-state resistance (Ron-sp) and electrical safe-operating area (SOA) by means of Technology Computer-Aided Design (TCAD) numerical simulations. The evolution of the measured and simulated VBR as a function of the substrate (handle wafer) voltage (HWV) gives good physical insight of the optimal LDNMOS drift region design configuration. LDNMOS transistors with STI lengths partially covering the drift region length leads to better combined action of Ron-sp/VBR trade-off and electrical SOA results.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
