Design and optimization of high voltage LDMOS transistors on 0.18 μm SOI CMOS technology

Abstract

This paper analyses the voltage capability of lateral power ( V BR > 120 V) P- and N-channel MOS transistors manufactured on a 0.18 μm SOI CMOS technology by means of TCAD numerical simulations. The measured breakdown voltage results as a function of the handle wafer voltage of power LDMOS transistors are compared with TCAD numerical simulation with the purpose of understanding the problems arising in the measured structures. Some important design parameters such as the STI length ( L STI) and technological concerns like the P-well and N-well doping profiles have a strong influence on the voltage capability. As a consequence, some design solutions are proposed in this work to improve the performances of the fabricated LDMOS structures.