Μm SOI CMOS Process Research Articles

Characterization and Modeling of a Highly Reliable ONO Antifuse for High-Performance FPGA and PROM

The characteristics and reliability of ONO (oxide-nitride-oxide) anti-fuse devices prepared basing on 0.6µm SOI CMOS process have been studied experimentally and theoretically. The intrinsic principles of ONO dielectric breakdown were investigated with tunneling and emission models. It has been found that the conduction mechanisms of ONO dielectrics under high electric field (>10MV/cm) mainly obeys Fowler-Nordheim (F-N) tunneling and Poole-Frenkel (P-F) emission and Ohmic transport models. Meanwhile, the nitrogen depth distribution and the composition of the ONO stack films have been accurately determined using SIMS and EDX, respectively. The results indicate that the nitrogen concentration of interface between tunneling oxide and N+ sub-silicon is higher than that of interface between top oxide and N+ poly-silicon, which can contribute to prove the difference of top and bottom electrode interface barriers according to energy band diagrams of ONO anti-fuse devices. Besides, it is also found that the average breakdown voltage of ONO anti-fuse arrays and that of distribution decrease with increasing the number of anti-fuse cells, and the result is attributed to traps density of various areas. Moreover, the programming resistance of ONO anti-fuse cells and programming circuits decreases with increasing programming current, and the programming resistance of ONO anti-fuse cells can reach less than 200 ohm/cont when programming current is above 5mA. And the life of unprogrammed ONO anti-fuse devices can reach more than 40 years under an electric stress of 5.5v at the temperature from 25°C to 125°C. So, it can be concluded that the characteristics and reliability of the proposed ONO anti-fuse elements are suitable for applications in FPGA and PROM.

A Highly Linear 1 GHz 1.3 dB NF CMOS Low-Noise Amplifier With Complementary Transconductance Linearization

A highly linear LNA is implemented in a 0.18 µm SOI CMOS process for 1 GHz SAW-less receiver applications. To achieve lower noise figure (NF) than conventional simultaneous noise and input matching methods, a capacitive loading based simultaneous noise and input matching technique reducing the NF degradation coming from a lossy gate inductor has been devised. In addition, in order to improve both the 1 dB gain compression point (CP1dB) and the third-order intercept point (IP3) without sacrificing NF, a large-signal transconductance linearization method adopting body-bias control and complementary-superposition is proposed. The proposed LNA shows a measured input-referred CP1dB of 3 dBm, 1 dB desensitization point (B1dB) of 0 dBm and IB (in-band)-IIP3 of 22 dBm with gain of 10.7 dB and NF of 1.3 dB at 1 GHz while driving a 50 Ω load impedance. It draws 20 mA with a buffer stage from a 2.5 V supply voltage.

Reliability Investigations up to 350°C of Gate Oxide Capacitors Realized in a Silicon-on-Insulator CMOS Technology

It is difficult to use standard bulk-CMOS-technology at temperatures higher than 175°C due to high pn-leakage currents. Silicon-on-insulator-technologies (SOI), on the other hand, are usable up to 250°C and even higher, because leakage currents can be reduced by two to three orders of magnitude. Nevertheless, performance and reliability of SOI devices are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350°C. The experiments were carried out on gate oxide capacitor structures realized in the Fraunhofer 1.0 μm SOI-CMOS process. The gate oxide thickness is 40 nm. Using the data of the TDDB measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350°C was evaluated. For a more detailed investigation, the evolution of the current in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250°C, and make it possible to quickly evaluate the reliability of high temperature CMOS technologies at operation temperature.

Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style

Full adder is one of the most important digital components for which many improvements have been made to improve its architecture. In this paper, we present two new symmetric designs for Low-Power full adder cells featuring GDI (Gate-Diffusion Input) structure and hybrid CMOS logic style. The main design objectives for these adder modules are not only providing Low-Power dissipation and high speed but also full-voltage swing.In the first design, hybrid logic style is employed. The hybrid logic style utilizes different logic styles in order to create new full adders with desired performance. This provides the designer with a higher degree of design freedom to target a wide range of applications, hence reducing design efforts. The second design is based on a different new approach which eliminates the need of XOR/XNOR gates for designing full adder cell and also by utilizing GDI (Gate-Diffusion-Input) technique in its structure, it provides Ultra Low-Power and high speed digital component as well as a full voltage swing circuit.Many of the previously reported adders in literature suffered from the problems of low-swing and high noise when operated at low supply voltages. These two new designs successfully operate at low voltages with tremendous signal integrity and driving capability. In order to evaluate the performance of the two new full adders in a real environment, we incorporated two 16-bit ripple carry adders (RCA). The studied circuits are optimized for energy efficiency at 0.13µm and 90nm PD SOI CMOS process technology. The comparison between these two novel circuits with standard full adder cells shows excessive improvement in terms of Power, Area, Delay and Power-Delay-Product (PDP).

High Temperature Reliability Investigations up to 350 °C of Gate Oxide Capacitors realized in a Silicon-on-Insulator CMOS-Technology

Standard Bulk-CMOS-technology targets use-temperatures of not more than 175 °C. With Silicon-on-Insulator-technologies (SOI), digital and analog circuitry is possible up to 250 °C and even more, but performance and reliability are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350 °C. The experiments were carried out on gate oxide capacitor structures which were realized in the Fraunhofer 1.0 μm SOI-CMOS process. This technology is based on 200 mm wafers and features, among others, three layers of tungsten metallization with excellent reliability concerning electromigration, voltage independent capacitors, high resistance resistors, and single-poly-EEPROM cells. The gate oxide thickness is 40 nm. Using the data of the TDDB-measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350 °C was evaluated. For a more detailed investigation, the current evolution in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250 °C, and make it possible to quickly evaluate the reliability of high temperature CMOS-technologies at use-temperature.

A novel pLEDMOS device with large current capability and high reliability for PDP scan driver IC

A novel p-type lateral extended drain MOS (pLEDMOS) based on an SOI substrate has been presented for plasma display panels scan driver IC. By introducing a reversed doped high-voltage-Nwell that fabricated by the special SOI process, both the current capability and off-state breakdown voltage (BV) of the device are optimized well. The saturation current density over 0.6 mA µm−1 and the BV over 210 V for the novel pLEDMOS are achieved by using a 0.5 µm SOI CMOS process. Moreover, the hot-carrier degradation has also been improved compared with the conventional device.

A Robust SOI Gain-Boosted Operational Amplifier Targeting High Temperature Precision Applications up to 300°C

Data acquisition and signal processing at elevated temperatures are facing various problems due to a wide temperature range operation, affecting the accuracy of the circuits' references and elementary building blocks. As the most commonly used analog building block, the operational amplifier (op-amp) with its various limitations has to be enhanced for wide temperature range operation. Thereby major effort is put into maximizing signal gain and simultaneously reaching high gain-bandwidth also for high temperatures. Future robust design approaches have to consider a growing operating temperature range and increasing device parameter mismatch due to the downsizing of integrated circuits. Addressing one of the major problems in circuit design for the next decades, compensating these effects through new design approaches will have a lasting impact on circuit design. In this paper we present a high gain operational amplifier with a folded-cascode and gain-boosted input stage, fabricated in a 1.0 μm SOI CMOS process. The operational amplifier was designed for an operating temperature range of −40…300°C. Major effort was put into a robust design approach with reduced sensitivity to temperature variations, targeting high precision applications in a high temperature environment. With a supply voltage of 5 V, the maximum simulated current consumption of the op-amp is 210 μA which leads to overall maximum power consumption of 1.05 mW. The open loop DC gain of the amplifier is expected to reach a minimum of 108 dB and a unity-gain-frequency of 1.02 MHz at a temperature of 300°C. For all temperatures the phase margin varies from 55…70 degrees for a 3 pF load.

Statistical optimization and manufacturing sensitivity analysis of 0.18 μm SOI MOSFETs

A comprehensive approach based on TCAD and statistical methods has been demonstrated for deep submicron SOI CMOS process optimization and manufacturing sensitivity analysis. Second-order response surface models were fitted to ten device characteristics based on 15 processing conditions identified as significantly affecting the CMOS process. The optimized 0.18 μm SOI CMOS process, representative of deep submicron SOI technology currently under consideration by industry, was determined by numerical analysis of the generated models. A two part sensitivity analysis was then conducted for the optimized process. A Monte Carlo analysis technique was applied to a set of reduced response models to determine the sensitivity of the device characteristics to some anticipated manufacturing process random variations. Results for a 0.18 μm PD SOI CMOS technology are presented, providing optimized process conditions meeting desired device performance measures, and indicating no conspicuous device performance degradation by anticipated manufacturing process variations.