Μm High Voltage CMOS Technology Research Articles

Multi-Channel Gating Chip in 0.18 µm High-Voltage CMOS for Quantum Applications.

A gating circuit for a photonic quantum simulator is introduced. The gating circuit uses a large excess bias voltage of up to 9.9 V and an integrated single-photon avalanche diode (SPAD). Nine channels are monolithically implemented in an application-specific integrated circuit (ASIC) including nine SPADs using 0.18 µm high-voltage CMOS technology. The gating circuit achieves rise and fall times of 480 ps and 280 ps, respectively, and a minimum full-width-at-half-maximum pulse width of 1.26 ns. Thanks to a fast and sensitive comparator, a detection threshold for avalanche events of less than 100 mV is possible. The power consumption of all nine channels is about 250 mW in total. This gating chip is used to characterize the integrated SPADs. A photon detection probability of around 50% at 9.9 V excess bias and for a wavelength of 635 nm is found.

Siwa: A custom RISC-V based system on chip (SOC) for low power medical applications

This work introduces the development of Siwa, a RISC-V RV32I 32-bit based core, intended as a flexible control platform for highly integrated implantable biomedical applications, and implemented on a commercial 0.18 μm high voltage (HV) CMOS technology. Simulations show that Siwa can outperform commercial micro-controllers commonly used in the medical industry as control units for implantable devices, with energy requirements below the 50 pJ per clock cycle.

An ASIC for Recording and Stimulation in Stacked Microchannel Neural Interfaces.

This paper presents an active microchannel neural interface (MNI) using seven stacked application specific integrated circuits (ASICs). The approach provides a solution to the present problem of interconnect density in three-dimensional (3-D) MNIs. The 4 mm2 ASIC is implemented in 0.35 μm high-voltage CMOS technology. Each ASIC is the base for seven microchannels each with three electrodes in a pseudo-tripolar arrangement. Multiplexing allows stimulating or recording from any one of 49 channels, across seven ASICs. Connections to the ASICs are made with a five-line parallel bus. Current controlled biphasic stimulation from 5 to 500 μA has been demonstrated with switching between channels and ASICs. The high-voltage technology gives a compliance of 40V for stimulation, appropriate for the high impedances within microchannels. High frequency biphasic stimulation, up to 40 kHz is achieved, suitable for reversible high frequency nerve blockades. Recording has been demonstrated with mV level signals; common-mode inputs are differentially distorted and limit the CMRR to 40 dB. The ASIC has been used in vitro in conjunction with an oversize (2mm diameter) microchannel in phosphate buffered saline, demonstrating attenuation of interference from outside the microchannel and tripolar recording of signals from within the microchannel. By using five-lines for 49 active microchannels the device overcomes limitations when connecting many electrodes in a 3-D miniaturized nerve interface.

A High-Efficiency Low-Power Chip-Based CMOS Liquid Crystal Driver for Tunable Electro-Optic Eyewear

A high-efficiency low-power chip-based liquid crystal (LC) driver has been successfully designed and implemented for adaptive electro-optic eyewear including tunable vision correction devices (eyeglass, contact lens, intraocular lens, occluder, and prism), phoropter, iris, head-mounted display, and 3D imaging. The driver can generate a 1 kHz bipolar square wave with magnitude tunable from 0 V to 15 V to change the lens focus adaptively. The LC driver output magnitude is controlled by a reference DC voltage that is manually tunable between 0 and 3 V. A multi-mode 1×/2×/3×/4×/5× charge pump is developed for DC-DC conversion to expand the output range with a fast-sink function implemented to regulate the charge pump output. In addition, a new four-phase H-bridge driving scheme is employed to improve the DC/AC inverter efficiency. The LC driver has been successfully implemented and tested as an IC chip (8.6 mm × 8.6 mm) using AMS 0.18 μm High-Voltage CMOS technology.

A Hybrid Readout Solution for GaN-Based Detectors Using CMOS Technology.

Gallium nitride (GaN) and its alloys are becoming preferred materials for ultraviolet (UV) detectors due to their wide bandgap and tailorable out-of-band cutoff from 3.4 eV to 6.2 eV. GaN based avalanche photodiodes (APDs) are particularly suitable for their high photon sensitivity and quantum efficiency in the UV region and for their inherent insensitivity to visible wavelengths. Challenges exist however for practical utilization. With growing interests in such photodetectors, hybrid readout solutions are becoming prevalent with CMOS technology being adopted for its maturity, scalability, and reliability. In this paper, we describe our approach to combine GaN APDs with a CMOS readout circuit, comprising of a linear array of 1 × 8 capacitive transimpedance amplifiers (CTIAs), implemented in a 0.35 µm high voltage CMOS technology. Further, we present a simple, yet sustainable circuit technique to allow operation of APDs under high reverse biases, up to ≈80 V with verified measurement results. The readout offers a conversion gain of 0.43 µV/e−, obtaining avalanche gains up to 103. Several parameters of the CTIA are discussed followed by a perspective on possible hybridization, exploiting the advantages of a 3D-stacked technology.

A 700 MHz laser radar receiver realized in 0.18 μm HV-CMOS

This study presents a CMOS receiver chip realized in 0.18 µm High-Voltage CMOS (HV-CMOS) technology and intended for high precision pulsed time-of-flight laser range finding utilizing high-energy sub-ns laser pulses. The IC chip includes a trans-impedance preamplifier, a post-amplifier and a timing comparator. Timing discrimination is based on leading edge detection and the trailing edge is also discriminated for measuring the width of the pulse. The transimpedance of the channel is 25 kΩ, the uncompensated walk error is 470 ps in the dynamic range of 1:21,000 and the input referred equivalent noise current 450 nA (rms).

A 4 × 128 SPAD array with a 78-ps 512-channel TDC for time-gated pulsed Raman spectroscopy

A time-gated 4 × 128 single photon avalanche diode (SPAD) line array with a 512-channel time-to-digital converter (TDC) has been designed and fabricated in a 0.35 µm high voltage CMOS technology for pulsed Raman spectroscopy. In Raman spectroscopy the SPAD array can be designed as a line array with a high fill factor because the electronics can be placed on either side of it. The resolution of the designed TDC is 80 ps in the first four bins, to achieve an accurate time position of the Raman photons, while the last four bins are increased in width to achieve a larger dynamic range. The measured standard deviation of the variation in the width of the first four bins of the 512-channel TDC was less than 10 ps. In addition, cross-talk measurements were carried out to investigate the probability of cross-talk between adjacent SPADs in an array of high density. These showed a cross-talk probability of 0.12 % with a pitch of 32 µm between adjacent SPADs. The highest probability of cross-talk was found to occur with a short delay.

A Fully-Implantable Cochlear Implant SoC with Piezoelectric Middle-Ear Sensor and Arbitrary Waveform Neural Stimulation.

A system-on-chip for an invisible, fully-implantable cochlear implant is presented. Implantable acoustic sensing is achieved by interfacing the SoC to a piezoelectric sensor that detects the sound-induced motion of the middle ear. Measurements from human cadaveric ears demonstrate that the sensor can detect sounds between 40 and 90 dB SPL over the speech bandwidth. A highly-reconfigurable digital sound processor enables system power scalability by reconfiguring the number of channels, and provides programmable features to enable a patient-specific fit. A mixed-signal arbitrary waveform neural stimulator enables energy-optimal stimulation pulses to be delivered to the auditory nerve. The energy-optimal waveform is validated with in-vivo measurements from four human subjects which show a 15% to 35% energy saving over the conventional rectangular waveform. Prototyped in a 0.18 μm high-voltage CMOS technology, the SoC in 8-channel mode consumes 572 μW of power including stimulation. The SoC integrates implantable acoustic sensing, sound processing, and neural stimulation on one chip to minimize the implant size, and proof-of-concept is demonstrated with measurements from a human cadaver ear.

A vestibular prosthesis with highly-isolated parallel multichannel stimulation.

This paper presents an implantable vestibular stimulation system capable of providing high flexibility independent parallel stimulation to the semicircular canals in the inner ear for restoring three-dimensional sensation of head movements. To minimize channel interaction during parallel stimulation, the system is implemented with a power isolation method for crosstalk reduction. Experimental results demonstrate that, with this method, electrodes for different stimulation channels located in close proximity ( mm) can deliver current pulses simultaneously with minimum inter-channel crosstalk. The design features a memory-based scheme that manages stimulation to the three canals in parallel. A vestibular evoked potential (VEP) recording unit is included for closed-loop adaptive stimulation control. The main components of the prototype vestibular prosthesis are three ASICs, all implemented in a 0.6- μm high-voltage CMOS technology. The measured performance was verified using vestibular electrodes in vitro.

A Compact Behavioral Simulation Model for CMOS Vertical Hall-Effect Devices

A compact behavioral simulation model for CMOS five-contact vertical Hall devices is presented. In term of the internal current flow geometry, the vertical Hall device is modeled based on an asymmetric Wheatstone bridge structure, including four current-controlled Hall voltage sources and four asymmetric lumped resistors. The lumped resistors on the Wheatstone bridge are calculated preliminarily by conformal mapping method. More importantly, the model takes into account the lateral diffusion effect and junction field effect which further improves the simulation accuracy. The behavioral model has been written in Verilog-A language with ten more physical and process parameters. The behavioral model simulation has been successfully performed in the Cadence Spectre environment with 0.8 μm high voltage CMOS technology parameters. The model’s simulation results are in good agreement with the reported experimental results.

A High Efficiency Orthogonally Switching Passive Charge Pump Rectifier for Energy Harvesters

The design and analytical modeling of a high efficiency energy harvester comprising a passive voltage-boosting network (VBN) and a switching charge pump rectifier (CPR) is presented in this paper. To improve the power conversion efficiency (PCE), the VBN increases the voltage at the input of the CPR and provides control signals for switching. Unlike traditional Schottky and diode-connected MOS transistor rectifiers, the proposed orthogonally switching CPR (OS-CPR) comprises MOS transistors as voltage-controlled switches. Analytical models for the OS-CPR are developed and presented. Circuit-level optimization techniques are employed to reduce conduction and switching losses. Simulated in a 90 nm standard CMOS technology (IBM 9RF), a 5-stage 915 MHz OS-CPR achieves a dc voltage of 1.35 V and a PCE of 11.9% with a 1 MΩ load at -18.2 dBm available input power ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S,AV</sub> ). To show technology scalability of the design, the OS-CPR is also validated using AMS 0.18 μm high-voltage (HV) CMOS technology. When benchmarked with traditional rectifiers, the OS-CPR (under similar conditions) achieves a higher PCE and a higher output dc voltage. The OS-CPR is easily scalable to operate over multiple sub-GHz ISM frequency bands.

31.1: A 3.5Gbps/Lane Intra‐panel Interface with a PVT‐robust VCO Based CDR for UD TV Applications in 0.18μm High‐voltage CMOS Technology

AbstractA CMOS voltage‐controlled oscillator (VCO) with robustness under PVT variation is proposed, and its application to a PLL‐based CDR is also presented. In the VCO design, voltage regulator is used to suppress voltage variation and improved voltage‐to‐current (V/I) converter is used to mitigate temperature variation and varactor‐tuned ring oscillator is used to reduce process variation. For broad bandwidth, comparator adopts the active negative feedback circuit and Signal Integrity (SI) on PCB channel is also improved considering via effect. Simulation and test results under 0.18‐μm high‐voltage CMOS technology show that the VCO output frequency range is from 300MHz to 700MHz and the maximum intra‐panel interface operating speed is up to 3.5Gbps per lane for UD LCD‐TV applications.

Low-noise single-photon avalanche diodes in 025 μm high-voltage CMOS technology

By using 0.25μm high-voltage CMOS technology, we have designed and fabricated a structure of single-photon detectors. The new single-photon avalanche diode (SPAD) has (to our knowledge) the lowest dark count rate per unit area at room temperature without any technology customization. Our design is promising for realizing low-cost and high-performance SPAD arrays for imaging applications.

A Highly Sensitive CMOS Digital Hall Sensor for Low Magnetic Field Applications

Integrated CMOS Hall sensors have been widely used to measure magnetic fields. However, they are difficult to work with in a low magnetic field environment due to their low sensitivity and large offset. This paper describes a highly sensitive digital Hall sensor fabricated in 0.18 μm high voltage CMOS technology for low field applications. The sensor consists of a switched cross-shaped Hall plate and a novel signal conditioner. It effectively eliminates offset and low frequency 1/f noise by applying a dynamic quadrature offset cancellation technique. The measured results show the optimal Hall plate achieves a high current related sensitivity of about 310 V/AT. The whole sensor has a remarkable ability to measure a minimum ±2 mT magnetic field and output a digital Hall signal in a wide temperature range from −40 °C to 120 °C.

An integrated signal conditioner for high-frequency inductive position sensors

This paper describes the design, implementation and evaluation of a signal conditioner application-specific integrated circuit (ASIC) for high-frequency inductive non-contact position sensors. These sensors employ a radio frequency technology based on an antenna planar arrangement and a resonant target, have a high inherent resolution (0.1% of antenna length) and can measure target position over a wide distance range (<0.1 mm to >10 m). However, due to the relatively high-frequency excitation (1 MHz typically) and to the specific layouts of these sensors, there is unwanted capacitive coupling between the transmitter and receiver coils; this type of distortion reduces linearity and resolution. The ASIC, which is the first generation of its kind for this type of sensor, employs a differential mixer topology which suppresses the capacitive coupling offsets. The system architecture and circuit details are presented. The ASIC was fabricated in a 0.6 µm high-voltage CMOS technology occupying an area of 8 mm2. It dissipates about 30 mA from a 24 V power supply. The ASIC was tested with a high-frequency inductive position sensor (with an antenna length of 10.8 cm). The measured input-referred offset due to transmitter crosstalk is on average about 22 µV over a wide phase difference variation (−99° to +117°) between the transmitter and demodulating signals.

A CMOS Time-Resolved Fluorescence Lifetime Analysis Micro-System.

We describe a CMOS-based micro-system for time-resolved fluorescence lifetime analysis. It comprises a 16 × 4 array of single-photon avalanche diodes (SPADs) fabricated in 0.35 μm high-voltage CMOS technology with in-pixel time-gated photon counting circuitry and a second device incorporating an 8 × 8 AlInGaN blue micro-pixellated light-emitting diode (micro-LED) array bump-bonded to an equivalent array of LED drivers realized in a standard low-voltage 0.35 μm CMOS technology, capable of producing excitation pulses with a width of 777 ps (FWHM). This system replaces instrumentation based on lasers, photomultiplier tubes, bulk optics and discrete electronics with a PC-based micro-system. Demonstrator lifetime measurements of colloidal quantum dot and Rhodamine samples are presented.

Scalable High Voltage CMOS technology for Smart Power and sensor applications

Integration of low voltage analog and logic circuits as well as high-voltage (HV) devices for operation at greater than 5 V enables Smart Power ICs used in almost any system that contains electronics. HVCMOS (High-Voltage CMOS) technologies offer much lower process cost, if compared to BCD technologies, they enable multiple HV levels on a single chip, and need less effort when scaling to smaller CMOS technology nodes or when integrating embedded non-volatile memory. In this work we propose a new 0.35 µm HVCMOS technology that can overcome the previous limitations in drive currents. It can match the low HV chip sizes (Rdson) of typical BCD processes while maintaining the low process complexity with only 2 mask level adders on top of CMOS. We also introduce a figure of merit (FOM) for comparing HV technologies. Key elements of making this newly proposed 0.35 µm HVCMOS so competitive to BCD technologies are discussed and a device lifetime of more than 10 years, operating temperatures of 150 °C and ESD robustness of 4 kV HBM and higher, as well as the integration of a highly robust embedded EEPROM/Flash technology is shown. We also provide first verification results of the scalability of the proposed 0.35 µm HVCMOS technology to 0.18 µm and beyond as well as to currents of up to 8 A.