31.1: A 3.5Gbps/Lane Intra‐panel Interface with a PVT‐robust VCO Based CDR for UD TV Applications in 0.18μm High‐voltage CMOS Technology

Abstract

AbstractA CMOS voltage‐controlled oscillator (VCO) with robustness under PVT variation is proposed, and its application to a PLL‐based CDR is also presented. In the VCO design, voltage regulator is used to suppress voltage variation and improved voltage‐to‐current (V/I) converter is used to mitigate temperature variation and varactor‐tuned ring oscillator is used to reduce process variation. For broad bandwidth, comparator adopts the active negative feedback circuit and Signal Integrity (SI) on PCB channel is also improved considering via effect. Simulation and test results under 0.18‐μm high‐voltage CMOS technology show that the VCO output frequency range is from 300MHz to 700MHz and the maximum intra‐panel interface operating speed is up to 3.5Gbps per lane for UD LCD‐TV applications.