A VCO with high supply noise rejection and its application to PLL frequency synthesizer

Abstract

A CMOS voltage-controlled oscillator (VCO) with high supply noise rejection is designed, and its application to a phase-locked loop (PLL) frequency synthesizer is also presented. In the VCO design, voltage regulator is used to suppress high and low frequency noise by isolation from power supply and to make stable internal voltage for oscillator; dual-path oscillator is adopted and a modification is made in voltage-current converter to extend the VCO voltage-frequency convert linearity range. Other circuits in the PLL are also designed from the low noise perspective. Simulation results under 0.2 /spl mu/m TSMC CMOS process show that the VCO output frequency ranged from 0.234 GHz to 2.57 GHz, with control voltage turning range of 81% and linearity of 5.8%, 1 V supply voltage change induces 1.5 ps VCO period change when its output frequency is at 1.8 GHz; the PLL has a frequency range of 0.338 GHz to 2.26 GHz, and with 22 ps peak-to-peak jitter at 1.8 GHz.